cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Jwilson
Visitor
Visitor
626 Views
Registered: ‎11-11-2020

RFSoC output data rates

Jump to solution

Hi,

Wanted to make sure I am thinking about this correctly. I am looking at Gen3 RFSoC with a 5.0GSPS sample rate and a 14-bit ADC. Lets just say to make it easy for calculations that I wanted to look at the absolute maximum data rate coming out of the RFSoC. So with no decimation is my data rate coming out of the RFSoC simply 5.0GSPS x 14-bits= 70Gbps ? Are there additional bits in the data format for other parameters beyond the ADC bit count? 

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
klumsde
Moderator
Moderator
471 Views
Registered: ‎04-18-2011

Yes the premise is correct except the maximum decimation is x40 in the DDC.

The bit rate is (adc_fs/decimation) x16bit

The IP will arrange it in sample per axi stream word so that you can manage how many samples you get in parallel and therefore the clock requirement on the streaming interface 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

4 Replies
pthakare
Moderator
Moderator
573 Views
Registered: ‎08-08-2017

Hi @Jwilson 

Its parallel output so the effective data rate coming out of ADC is 5.0 Gbps only.

Each word interface to the RF-DAC and RF-ADC is 16 bits wide, even though the RF-DAC resolution is 14 bits and the RF-ADC 12 bits in Gen1 and 14 bits in Gen3.

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos
klumsde
Moderator
Moderator
561 Views
Registered: ‎04-18-2011

Hi @Jwilson @pthakare 

The ADC data on the fabric side comes out of the FIFO arranged in samples per word. 

So with the Maximum Sample rate on the ADC with the DDC bypassed (no decimation) you will be mandated to have 8 samples per word so the fabric clock rate going to be 625Mhz , challenging for timing I would say. 

Remember, the ADC sample rate here is not really the end goal. Higher ADC sample rates where we oversample the data achieve higher noise performance primarily and allow for more relaxed filtering in the analog domain. So there is usually some down sampling to fit into the wireless system, which will relax the PL fabric clock requirement 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Jwilson
Visitor
Visitor
532 Views
Registered: ‎11-11-2020

I think my choice of example is bad in this case. I was really trying to come up with analog bandwidth vs. storage requirements. With a more practical example lets say I have 5.0GSPS sample rate and 100x decimation. That should give me a bandwidth of about 20MHz if did the math right. So in that case is my data output 5.0GSPS/100x=50MSPS x 16bits = 80Mbps ? 

0 Kudos
klumsde
Moderator
Moderator
472 Views
Registered: ‎04-18-2011

Yes the premise is correct except the maximum decimation is x40 in the DDC.

The bit rate is (adc_fs/decimation) x16bit

The IP will arrange it in sample per axi stream word so that you can manage how many samples you get in parallel and therefore the clock requirement on the streaming interface 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post