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Visitor
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Registered: ‎08-22-2020

RFSoC simple DAC project with a DDR interface

Hi There,

I am using ZCU111 RFSoC evaluation board.

I am trying to get my head around it as it is a bit complex piece and I was playing with the out of the box rftool and doing small C projects with the existing hardware xsa and using Petalinux to control the DACs.

 

My question is , I am trying to design a system that generates synchronized output from multiple DACs and I need to design the hardware first. The thing is I tried to search for a simple 1 DAC and 1 DDR with 1 DMA example but couldn't find any example design to start.

 

Is there any simple design to control 1 DAC as a start that reads from a DDR memory using the Zynq processor to write the samples and streaming these samples from the DAC?

And if there is a sample HW/SW project where can I start as simple as possible so that I can extend it to stream 2 banks of samples to 2 DACs in the same time.

 

I know this is quite a comprehensive question, but I am very keen to understand how to design the hardware around the DACs to be able to control it from the Zynq processor using Petalinux.

 

Any help or hints is much appreciated.

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Advisor
Advisor
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Registered: ‎01-28-2008

Hi @BNicola 

  There's a reference design for the ZCU111 that moves data from the host to the DACs but as far as I recall, it doesn't buffer the data in DDR memory. The task you have in mind is quite complex so I doubt there'll be a simple example to do it.

 I would suggest you look into Pynq for ZCU111 as they have some interesting infrastructure to handle a project like you envision. https://github.com/Xilinx/ZCU111-PYNQ

 

Thanks,

-Pat

 

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Visitor
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Registered: ‎08-22-2020

Hi Pat,

Thanks for your reply.

Can you guide me for the example (from host to DAC) you mentioned and where is it located please ?

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Advisor
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Registered: ‎01-28-2008

Hi @BNicola 

  This may be the design you've been using, i.e. rftool

  https://www.xilinx.com/member/forms/download/design-license-xef.html?filename=rdf0476-zcu111-rf-dc-eval-tool-2020-1.zip

 

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

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Visitor
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Registered: ‎08-22-2020

So in short there is no way I can even dedicate a memory for each DAC and try to get the processor to fill them up using software for the DACs to stream out ?

question.png

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Visitor
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Registered: ‎08-22-2020

Or in Short, Can I write a simple 1024 buffer of samples (in hardware using Verilog) and feed the result directly to the DACs input? I think I will need to package my buffer in this case as an AXI compatible module, but is this other approach possible ??

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Advisor
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Registered: ‎01-28-2008

Hi @BNicola 

  You could write a module to source data directly to the RF DC component, as you described. You could also use a DDS compiler IP to generate a sine wave and use software to change its frequency for instance. Also keep in mind, there might be software needed to program the RF DC IP and board clocks as well, in order to achieve MTS (multi tile synchronization).

 

Thanks,

-Pat

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

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Visitor
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Registered: ‎08-22-2020

Thanks a lot Pat,

So just to be clear on your last bit of the RF DC IP and clocking bit software, is this tight to the current Xilinx (out of the box) implementation ? or this is generic to the board and the Rfdc IP module??.

Because if so, I can still use their libraries to initialize the RFDC module and use simple IOs to connect to my buffers to write samples there.

Is that correct ?

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