05-13-2021 09:23 AM
I have a customer board with ZU48DR on it.
I'm trying to evaluate it and have build a single channel DAC projects at 6.4G and 1.6G respectively.
The simulation looks fine on both rates and see the data pattern going to DAC AXI4 interfaces.
1. could not see the ila after programming the FPGA - I've implemented a AXI Lite ila to monitor axi lite interface s_axi_
2. there is clock out from the RF data converter module - I've connected it to a connector with Freq at 1/8 of the AXI4 clock.
3. about the constraints of DAC_CLK_P/N_228 and SYSREF_P/N_228,
(1) - how to set the IO standard
(2) - was it enough by doing set_property LOC R5 [ get_ports dac0_clk_clk_p] and set_property LOC R4 [ get_ports dac0_clk_clk_n]?
05-16-2021 11:31 PM
#1 Can you please share the block diagram here ?
#2 Is the counter not running as intended ?
#3 Here the constraints are not required , required constraints for SYEREF and Sampling clock are taken care in IP constraints file.
05-17-2021 09:11 AM
I'm testing DAC0 at single channel (Tile 228) right now.
The DAC clock pins are R5/R4 while SYSREF are U5/U4.
I enabled the Clock Out and set the Freq to be 1/4 of Fabric Clock when configuring the IP.
For example, it's 100Mhz for 400MHz Fabric Clock with 6.4Gsps sampling rate.
I use this clock for a counter and put an output divided version to a SMA.
However there is not clock output observed.
OK, not constraints in my xdc file for DAC Clock and SYSREF as you said they are taking care by the IP.
05-17-2021 09:42 AM
Please share the block diagram to check on Clocks and reset connections.
05-18-2021 04:08 AM
Couple of points based on design block diagram shared
#1 Driving the AXI lite clock from Clocking wizard is fine
#2 AXI4 stream clock should be come from common source for Sampling clock and Stream clock
#3 What is the reference input to clocking wizard , make sure that clean reference is provided to have MMCM/PLL locked.
05-20-2021 12:17 PM
Found out why no DAC output. Because there is CLK_DAC0 outptu from the Core even the AXI4 streaming interface is OK.
My IP core is using the direct sampling clock in, which means that no PLL.
I've checked the register that DAC0_CLK has been detected, which means that sampling clock present.
Was any specific configuration needed to be done? Thanks.