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aherson
Contributor
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Registered: ‎01-05-2012

RX_BITSLICE 0 of High Speed SelectIO Wizard

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Hello,

 

I am using the Kintex US 040 with the High Speed IO Wizard in Vivado 2015.1 to create a 32 bit LVDS parallel bus across two banks, bank 44 and bank 45.  I am using "External Clock" .  I am trying to select pin pairs to best support a clean layout with minimum vias and trace issues.

 

The problem that I am having is that I simply do not understand why certain Interface combinations throw an error whereas others do not.  Specifically, I see "Please connect IO to bitslice 0 position".  Why?  Where is the bitslice 0 position?  Are these the "N0" pins in a byte lane?

 

Are they marked in ug575-ultrascale-pkg-pinout.pdf?  Unfortunately, I cannot find informtation on this in pg188-hig-speed-selectIO-wiz.pdf either.

 

Also, when I try to create a bus with less than 2 bytes worth of bits, I see many LVDS pair hidden from the drop down.  For example, Bank 68, 13-bit wide bus excludes the option to use A14/B14.  Why?

 

Finally, for those willing to help, note that the drop down selecters really benefit from going from the default pin -> none ->selection.  Chosing a previously selected location creates a scenario that is hard to escape from.

 

Thank You,

A

bit_slice_0.png
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aherson
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Registered: ‎01-05-2012

Fixed in 2015.3.

 

Thank You,

A

View solution in original post

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pulim
Xilinx Employee
Xilinx Employee
11,909 Views
Registered: ‎02-16-2014

hi @aherson

 

Silicon has a limitation such that All native interfaces require bitslice[0] to be connected to bitslice control.

From the error message it seems the bitslice0 in the bitslice control 6 is not being used.

 

By default, HSSIO wizard selects the IOs so that bitslice0 in the bitslice control will be used.

One quick check you can do is , generate the IP with default options and open the example design and implement it.

 

You can open the implemented design and mark the I/Os and in the device view you can check that bitslice0 will be used in every bitslice control.

 

WIth this you can cross-check the pin planning that you are choosing.

 

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aherson
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Registered: ‎01-05-2012

Hi There,

 

I have found in ug571-ultrascale-selectio.pdf page 263 the the letters QBC mark bitslice 0 in most cases.  So, I have successfully modified my XDC file to support that.  Now I see:

 

[Place 30-689] Failed to place BITSLICE_CONTROL cell design_1_wrapper_inst/design_1_i/twelve_bit_interface_1/inst/bank_44_45_inst/inst/if1_bitslice_control_array_inst/nibble_5_bitslicectrl on site BITSLICE_CONTROL_X0Y13 because Instance design_1_wrapper_inst/design_1_i/twelve_bit_interface_1/inst/bank_44_45_inst/inst/if1_bitslice_control_array_inst/nibble_5_bitslicectrl can not be placed in CONTROL of site BITSLICE_CONTROL_X0Y13 because the bel is occupied by design_1_wrapper_inst/design_1_i/twelve_bit_interface_1/inst/bank_44_45_inst/inst/if1_bitslice_control_array_inst/nibble_1_bitslicectrl. This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.

 

I do not understand the message.  When I open up the impemented Device, I see that X0Y13 is blank and far away from the nearest IO pin in the bank.

 

Thank You,

A

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pulim
Xilinx Employee
Xilinx Employee
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Registered: ‎02-16-2014

Hi @aherson

 

Glad that you were able to LOC the I/O to bitslice0 now.

 

From the error messgae it seems BITSLICE_CONTROL_X0Y13 is already occupied by nibble1 and to the same BITSLICE_CONTROL_X0Y13 you are trying to LOC the bitslicectrl of nibble5.

 

Can you open the synthesized design and cross check on this?

 

If you can share the project with me I can check on this issue.

 

 

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pulim
Xilinx Employee
Xilinx Employee
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Registered: ‎02-16-2014

Hi @aherson

 

Did you check on this?

If you are still seeing the issue please share the design.

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aherson
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Registered: ‎01-05-2012

Hi @pulim,

 

Attached is my example design with the IP block.  You can move pins around a little if you have to.

 

Thank You,

A

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pulim
Xilinx Employee
Xilinx Employee
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Registered: ‎02-16-2014

hi @aherson

 

Your customIP files are missing in the project , due to this I am not able to implement the design.

Can you archive the files properly incluidng custom IP files and send them again?

 

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aherson
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Registered: ‎01-05-2012

Hi @pulim

 

Geez.  Frustrarting!

 

I see this message when I archive

 

[Common 17-680] Path length exceeds 260-Byte maximum allowed by Windows: C:/Users/<name here>/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4448-<user>/PrjAr/_X_/twelve_bit_ip_test.ipdefs/IP_0/12-bit/hi_speed_io_example_design/high_speed_selectio_wiz_0_example/high_speed_selectio_wiz_0_example.runs/impl_1/high_speed_selectio_wiz_0_exdes.tcl
Please consider using the OS subst command to shorten the path length by mapping part of the path to a virtual drive letter. See Answer Record AR52787 for more information.

But I have already mapped my project to an "r:" drive.  So I am a bit baffled by this.

 

Attached is my IP archived and my preferred constraints file.

 

Thank You,

Andrew

 

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aherson
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Registered: ‎01-05-2012

Hi @pulim,

 

Any update on this?


Thank You,

A

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aherson
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Registered: ‎01-05-2012

Hi @pulim

 

Attached is a properly archived project to test.

 

(I had to reinstall 2015.2.1).

 

Thank You,

A

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aherson
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Registered: ‎01-05-2012

Hi @pulim

 

Can you please help this get solved in the next Vivado release?  Please let them know about all the strange GUI issues.

 

When is 2015.3 expected?

 

Thank You,

A

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aherson
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Registered: ‎01-05-2012

Fixed in 2015.3.

 

Thank You,

A

View solution in original post

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kelbyp
Xilinx Employee
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Registered: ‎02-03-2016

Hopefully you have also seen this AR: http://www.xilinx.com/support/answers/64216.html 

 

It is our master list for the known issues with the High Speed SelectIO Wizard.  We also have PG188.  Soon to be released XAPP1274 will also contain additional use cases with the wizard and additional information for native mode and SelectIO applications.  This will be the first release draft of this application note. 

 

This wizard has to support many different types of applications, which we are enhancing to help support those applications.  As with any new IP, we are working to fix any additional bugs we uncover. 

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rjen
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Registered: ‎11-01-2013

Hi there,

 

I'm very interessted in XAPP1274. I hope to get some more information how to design SelectIO-Interfaces with more than one bank.

Are there some updates for XAPP1274? Is there a fixed release date?

 

regards rob

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ngp22
Newbie
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5,597 Views
Registered: ‎01-09-2017

Hi Support Team,

 

Please let us know, if there is any update on Multi-Bank LVDS HSSIO usage.

 

Thanks,

Gokul

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kelbyp
Xilinx Employee
Xilinx Employee
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Registered: ‎02-03-2016

With 2017.1 we are releasing a version of the High Speed SelectIO wizard that has the right hooks needed for multi-bank support in UltraScale and UltraScale+ devices.  The challenge with this multi-bank solution is resource sharing.  For example, each bank has 2 dedicated PLLs that need to be synchronized across banks.  There are hooks from the HSSIO wizard wrapper that are connected between the two different IP in each separate bank and the reset state machines need to be synchronized.  You may need the PLL resources for other applications in a bank (i.e. memory), which you have the option to share.  There will initially be an AR that explains this multi-bank application, which is set to release soon.

 

For native mode (high performance) applications in the range of 300 - 1600 Mbps, applications and examples are being documented in XAPP1274.  This has been released for some time now, with a recent added update for asynchronous operation reference design in HDL.  There is an additional update planned for an asynchronous application using the HSSIO wizard, which will be added to XAPP1274.      

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kelbyp
Xilinx Employee
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Yes, we support it now.  See AR68620.  We also added a section in UG571 on multibank.

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mik3l3_hdl
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Registered: ‎08-15-2019

Hi ,

I am implementing a DAC interface for my top level design on Ultrascale VCU118 xcvu9p.

When I run the implementation i get this error message

  • [Place 30-685] Cell dacInterface/ABOut/inst/top_inst/bs_top_inst/u_tx_bs/TX_BS[25].u_tx_bitslice_if_bs is used in native BITSLICE mode, but it is not connected to any I/O ports. Please correct the design.

How to fix this?

 

Thanks

Regards

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mik3l3_hdl
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Registered: ‎08-15-2019

Hi @pulim ,

 

I am getting a similar error:

 

[Place 30-689] Failed to place BITSLICE_CONTROL cell dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst on site BITSLICE_CONTROL_X0Y15 because Instance dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst can not be placed in CONTROL of site BITSLICE_CONTROL_X0Y15 because the bel is occupied by dacInterface/ABOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst(port:). This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.

 

Could you please give me any hints?


Thanks

Regards

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