07-13-2015 12:25 AM
I am using the Kintex US 040 with the High Speed IO Wizard in Vivado 2015.1 to create a 32 bit LVDS parallel bus across two banks, bank 44 and bank 45. I am using "External Clock" . I am trying to select pin pairs to best support a clean layout with minimum vias and trace issues.
The problem that I am having is that I simply do not understand why certain Interface combinations throw an error whereas others do not. Specifically, I see "Please connect IO to bitslice 0 position". Why? Where is the bitslice 0 position? Are these the "N0" pins in a byte lane?
Are they marked in ug575-ultrascale-pkg-pinout.pdf? Unfortunately, I cannot find informtation on this in pg188-hig-speed-selectIO-wiz.pdf either.
Also, when I try to create a bus with less than 2 bytes worth of bits, I see many LVDS pair hidden from the drop down. For example, Bank 68, 13-bit wide bus excludes the option to use A14/B14. Why?
Finally, for those willing to help, note that the drop down selecters really benefit from going from the default pin -> none ->selection. Chosing a previously selected location creates a scenario that is hard to escape from.
07-16-2015 10:26 PM
Silicon has a limitation such that All native interfaces require bitslice to be connected to bitslice control.
From the error message it seems the bitslice0 in the bitslice control 6 is not being used.
By default, HSSIO wizard selects the IOs so that bitslice0 in the bitslice control will be used.
One quick check you can do is , generate the IP with default options and open the example design and implement it.
You can open the implemented design and mark the I/Os and in the device view you can check that bitslice0 will be used in every bitslice control.
WIth this you can cross-check the pin planning that you are choosing.
07-24-2015 10:44 PM - edited 07-25-2015 10:26 PM
I have found in ug571-ultrascale-selectio.pdf page 263 the the letters QBC mark bitslice 0 in most cases. So, I have successfully modified my XDC file to support that. Now I see:
[Place 30-689] Failed to place BITSLICE_CONTROL cell design_1_wrapper_inst/design_1_i/twelve_bit_interface_1/inst/bank_44_45_inst/inst/if1_bitslice_control_array_inst/nibble_5_bitslicectrl on site BITSLICE_CONTROL_X0Y13 because Instance design_1_wrapper_inst/design_1_i/twelve_bit_interface_1/inst/bank_44_45_inst/inst/if1_bitslice_control_array_inst/nibble_5_bitslicectrl can not be placed in CONTROL of site BITSLICE_CONTROL_X0Y13 because the bel is occupied by design_1_wrapper_inst/design_1_i/twelve_bit_interface_1/inst/bank_44_45_inst/inst/if1_bitslice_control_array_inst/nibble_1_bitslicectrl. This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.
I do not understand the message. When I open up the impemented Device, I see that X0Y13 is blank and far away from the nearest IO pin in the bank.
07-27-2015 09:39 AM
Glad that you were able to LOC the I/O to bitslice0 now.
From the error messgae it seems BITSLICE_CONTROL_X0Y13 is already occupied by nibble1 and to the same BITSLICE_CONTROL_X0Y13 you are trying to LOC the bitslicectrl of nibble5.
Can you open the synthesized design and cross check on this?
If you can share the project with me I can check on this issue.
07-29-2015 08:05 PM - edited 07-29-2015 08:06 PM
07-29-2015 11:43 PM - edited 07-29-2015 11:43 PM
07-31-2015 10:04 PM
I see this message when I archive
[Common 17-680] Path length exceeds 260-Byte maximum allowed by Windows: C:/Users/<name here>/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4448-<user>/PrjAr/_X_/twelve_bit_ip_test.ipdefs/IP_0/12-bit/hi_speed_io_example_design/high_speed_selectio_wiz_0_example/high_speed_selectio_wiz_0_example.runs/impl_1/high_speed_selectio_wiz_0_exdes.tcl Please consider using the OS subst command to shorten the path length by mapping part of the path to a virtual drive letter. See Answer Record AR52787 for more information.
But I have already mapped my project to an "r:" drive. So I am a bit baffled by this.
Attached is my IP archived and my preferred constraints file.
09-15-2015 10:36 PM
02-03-2016 06:22 PM
Hopefully you have also seen this AR: http://www.xilinx.com/support/answers/64216.html
It is our master list for the known issues with the High Speed SelectIO Wizard. We also have PG188. Soon to be released XAPP1274 will also contain additional use cases with the wizard and additional information for native mode and SelectIO applications. This will be the first release draft of this application note.
This wizard has to support many different types of applications, which we are enhancing to help support those applications. As with any new IP, we are working to fix any additional bugs we uncover.
02-28-2016 10:44 PM
I'm very interessted in XAPP1274. I hope to get some more information how to design SelectIO-Interfaces with more than one bank.
Are there some updates for XAPP1274? Is there a fixed release date?
04-11-2017 02:30 PM
With 2017.1 we are releasing a version of the High Speed SelectIO wizard that has the right hooks needed for multi-bank support in UltraScale and UltraScale+ devices. The challenge with this multi-bank solution is resource sharing. For example, each bank has 2 dedicated PLLs that need to be synchronized across banks. There are hooks from the HSSIO wizard wrapper that are connected between the two different IP in each separate bank and the reset state machines need to be synchronized. You may need the PLL resources for other applications in a bank (i.e. memory), which you have the option to share. There will initially be an AR that explains this multi-bank application, which is set to release soon.
For native mode (high performance) applications in the range of 300 - 1600 Mbps, applications and examples are being documented in XAPP1274. This has been released for some time now, with a recent added update for asynchronous operation reference design in HDL. There is an additional update planned for an asynchronous application using the HSSIO wizard, which will be added to XAPP1274.
08-18-2019 12:18 PM
I am implementing a DAC interface for my top level design on Ultrascale VCU118 xcvu9p.
When I run the implementation i get this error message
How to fix this?
08-20-2019 02:41 PM
Hi @pulim ,
I am getting a similar error:
[Place 30-689] Failed to place BITSLICE_CONTROL cell dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL.bs_ctrl_inst on site BITSLICE_CONTROL_X0Y15 because Instance dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL.bs_ctrl_inst can not be placed in CONTROL of site BITSLICE_CONTROL_X0Y15 because the bel is occupied by dacInterface/ABOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL.bs_ctrl_inst(port:). This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.
Could you please give me any hints?