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Observer
Observer
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Registered: ‎07-26-2018

Ramping up from Low Power to High Power States in Virtex UltraScale+

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Hi,

We have a large design that occupies most of the UltraScale+ logic and want to find out what is the recommended ramp time for progressively enabling all the modules so the board does not crash (if all the logic was turned on at one instant).

This is different from the power-on ramp, which is covered by the manuals (e.g. page 12, https://www.xilinx.com/support/documentation/data_sheets/ds923-virtex-ultrascale-plus.pdf).  The power on ramp is about going from 0V to 95% Vcc.  We are worried about when the board is already on (idle) and gets programmed with large design.  It is recommended to sequence the design such that it slowly increases the power requirements to max power instead of instantaneously doing so -- but it is unclear what is the timing requirement for how "slowly" to do it.

Thanks in advance for any help!

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Teacher
Teacher
319 Views
Registered: ‎07-09-2009
Where did you read " low power to max power states too quickly and crashing, according to what we read."

The FPGA is quiet capable of running at full throttle , assuming your power supply and your cooling is sufficient,

It is possible that your power supply is not capable of taking the power jump of all off to all on,
Id suggest you need to get a scope on the powers to the fpga, and see how much of a dip is cause by switching on the modules of your design ,

Then you will know how fast you can cycle up / down,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Teacher
Teacher
353 Views
Registered: ‎07-09-2009
what do you mean by enabling modules ?
A normaly way of power reducing a design is clock gating

When you first configure the FPGA, all power is applied, but design is held in reset by your code design, so low power,

Its up to your code as to when / what sections of the code are clock enabled at any one time,

It can be clock by clock if you want,
the power always stays applied the same to the chip,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Observer
Observer
333 Views
Registered: ‎07-26-2018

Hi

Thanks for the reply.  Our design has N modules (Mod0, Mod1, ..., ModN).  When bitstream is loaded all the modules are initially disabled (clock gated).  All the modules need to be enabled for the computation to be performed, and combined all modules use up most of the FPGA so they draw close to max power.  If we enable all the modules at once, then we may risk the board going from low power to max power states too quickly and crashing, according to what we read.  This means that Mod0, Mod1, etc. need to be enabled in sequence to 'ramp up' before all modules are on and computation can start.  We can get power estimates for each module.

Question is how to compute how fast each module can be enabled in sequence so we don't crash the board?  So far we can't find relevant information in voltage regulator or power suppy data sheets.

Thanks!

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Highlighted
Teacher
Teacher
320 Views
Registered: ‎07-09-2009
Where did you read " low power to max power states too quickly and crashing, according to what we read."

The FPGA is quiet capable of running at full throttle , assuming your power supply and your cooling is sufficient,

It is possible that your power supply is not capable of taking the power jump of all off to all on,
Id suggest you need to get a scope on the powers to the fpga, and see how much of a dip is cause by switching on the modules of your design ,

Then you will know how fast you can cycle up / down,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post