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shaikon
Voyager
Voyager
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Registered: ‎04-12-2012

Reading the part number from silicon

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Hello,

Do Ultrascale FPGAs have a hardcoded register that allows reading the full part number (including speed grade) ?

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653 Views
Registered: ‎01-22-2015

@shaikon 

Page 134 of UG570(v1.10) says that each UltraScale device has a unique device identifier (DNA) that can be read using the DNA_PORTE2 primitive.  See also the following AR that says a Xilinx barcode device is needed to interpret the DNA identifier.

https://www.xilinx.com/support/answers/71342.html

Information about Xilinx barcodes is given at the following site.

https://www.xilinx.com/support/answers/67513.html

Mark

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654 Views
Registered: ‎01-22-2015

@shaikon 

Page 134 of UG570(v1.10) says that each UltraScale device has a unique device identifier (DNA) that can be read using the DNA_PORTE2 primitive.  See also the following AR that says a Xilinx barcode device is needed to interpret the DNA identifier.

https://www.xilinx.com/support/answers/71342.html

Information about Xilinx barcodes is given at the following site.

https://www.xilinx.com/support/answers/67513.html

Mark

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shaikon
Voyager
Voyager
643 Views
Registered: ‎04-12-2012

What I wanted to do is decode the hardcoded number in runtime and make my logic run differently based on the speedgrade.

If the DNA requires an external tool - this doesn't seem possible.

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Registered: ‎01-22-2015

It seems unusual to postpone decisions that are based on speed-grade until the bitstream is loaded into the FPGA.  -since, changes in speed-grade typically cause changes in the bitstream.

That is, before running synthesis/implementation you must tell Vivado about the speed-grade of your part using a Tcl command something like the following.

set_property part xc7k160tfbg484-2 [current_project]

Since you must manually tell Vivado about the device speed-grade, it is reasonable that we should manually need to tell our HDL about the device speed-grade.  Unfortunately, I have found no way to query the “part” property of current_project and pass it to HDL.

In VHDL, we usually specify things like speed-grade using a global-constant in the VHDL package file for the project.  Then, VHDL components in the project use the global-constant in if-generate blocks (see pg193, UG901, v2019.1) to only synthesis HDL that is appropriate for the selected speed-grade.