I recently read xapp1330 and xapp1274 for using SelectIO in native mode. I also implemented xapp1330 (async data capture with HSSIO) and I have a question about data being captured in async native mode.
As I understood from the UG571 capturing data in async native mode is done with the phase alignment algorithm with sufficient delays on inputs and data is being deserialized in integrated FIFO. In the xapp1274 it is mentioned that data can be read with fifo_rd_clk input. When I look into design files of xapp1330 and xapp1274, I see this clock is generated through PLL which has freerun input clk and data is then processed with this pll0_clkout0.
Now my question is how is this clock synced with input data? What am I missing here?
When input rate increases a little bit, is there any routing (signal) between RX_BITSLICE and PLL that says PLL to increase output clock (pll0_clkout0)?