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Observer
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Registered: ‎01-13-2020

Reset \ Initialize in Ultrascale arch

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Hi all,

I am trying to understand the recommended ways to initialize and/or resetting registers.

FPGA in question: XCKU085

1. Is there a hardwired dedicated reset pin to Ultrascale FPGAs? I couldn't find any information about one in the UG575 "packaging and pinouts" paper. 

2. If so, could any pin act as a synchronized reset input?

3. If there is no reset connected to the design, how can I know what register's initial value is? What is the initialization process in that case?

4. according to U1026 "Ultrascale architecture migration" you could use the global set/reset (GSR) signal " implicitly specifying initialization of an inferred register" (page 10). with an example of : 


Capture.JPG

What exactly happens when I use the GSR signal? and how can I use it (the GSR signal)? Does it take anything else except for this coding practice?

5. I had an idea to connect the "locked" signal of my main clock PLL to the asynchronous reset signal. In this way, at startup, before "locked" arrives, the registers will be reset as well as any time. What could go potentially wrong with such a design?

All in all, I am not trying to achieve something unique, just trying to understand what is the best way to initial / set / reset registers, which coding practices it demands and which settings or other vivado tweaks I need to know.

Thank you!

 

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Registered: ‎01-22-2015

@adam_mira 

You will find there is not general agreement for handling the FPGA power-on reset. 

However, my thoughts on this are described in the following post, and they have served me well for many years.
https://forums.xilinx.com/t5/Versal-and-UltraScale/Impact-of-design-wide-asynchronous-resets-on-performance/m-p/1007016

The post referenced above will (I think) address all of your questions.  Below are some additional thoughts.

  1. Is there a hardwired dedicated reset pin to Ultrascale FPGAs? I couldn't find any information about one in the UG575 "packaging and pinouts" paper.
    No - although some would refer you to the GSR (Global Set/Reset) pin of the STARTUPE3 primitive - see page 118 of UG570(v1.11).

  2. If so, could any pin act as a synchronized reset input?
    A reset “trigger” can enter the FPGA on any general purpose IO pin - or it could be generated by something internal to the FPGA (as you suggest below).  I call it a “trigger” because it cannot by itself reset the design.  Instead, it can trigger HDL that you have written to reset the design.

  3. If there is no reset connected to the design, how can I know what register's initial value is? What is the initialization process in that case?
    As explained in the post referenced above, initialization and reset are different concepts.  I argue that a well designed power-on reset of the design is all that is needed - and that very often we do not need to know a register's initial value.

  4. according to U1026 "Ultrascale architecture migration" you could use the global set/reset (GSR) signal " implicitly specifying initialization of an inferred register" (page 10). with an example of :  What exactly happens when I use the GSR signal? and how can I use it (the GSR signal)? Does it take anything else except for this coding practice?
    As explained in the post referenced above, the GSR is not recommended for use in resetting the design because it has significant skew across the part.  This was true in 7-Series FPGAs and is apparently still true for UltraScale FPGAs as stated on page 118 of UG570(v1.11).

  5. I had an idea to connect the "locked" signal of my main clock PLL to the asynchronous reset signal. In this way, at startup, before "locked" arrives, the registers will be reset as well as any time. What could go potentially wrong with such a design?
    For many years, we have successfully use the "locked" output of the PLL/MMCM to trigger our dedicated-HDL that resets the design.  Please see the post that I referenced above and also read the EETIMES article referenced in that post.

Cheers,
Mark

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Highlighted
257 Views
Registered: ‎01-22-2015

@adam_mira 

You will find there is not general agreement for handling the FPGA power-on reset. 

However, my thoughts on this are described in the following post, and they have served me well for many years.
https://forums.xilinx.com/t5/Versal-and-UltraScale/Impact-of-design-wide-asynchronous-resets-on-performance/m-p/1007016

The post referenced above will (I think) address all of your questions.  Below are some additional thoughts.

  1. Is there a hardwired dedicated reset pin to Ultrascale FPGAs? I couldn't find any information about one in the UG575 "packaging and pinouts" paper.
    No - although some would refer you to the GSR (Global Set/Reset) pin of the STARTUPE3 primitive - see page 118 of UG570(v1.11).

  2. If so, could any pin act as a synchronized reset input?
    A reset “trigger” can enter the FPGA on any general purpose IO pin - or it could be generated by something internal to the FPGA (as you suggest below).  I call it a “trigger” because it cannot by itself reset the design.  Instead, it can trigger HDL that you have written to reset the design.

  3. If there is no reset connected to the design, how can I know what register's initial value is? What is the initialization process in that case?
    As explained in the post referenced above, initialization and reset are different concepts.  I argue that a well designed power-on reset of the design is all that is needed - and that very often we do not need to know a register's initial value.

  4. according to U1026 "Ultrascale architecture migration" you could use the global set/reset (GSR) signal " implicitly specifying initialization of an inferred register" (page 10). with an example of :  What exactly happens when I use the GSR signal? and how can I use it (the GSR signal)? Does it take anything else except for this coding practice?
    As explained in the post referenced above, the GSR is not recommended for use in resetting the design because it has significant skew across the part.  This was true in 7-Series FPGAs and is apparently still true for UltraScale FPGAs as stated on page 118 of UG570(v1.11).

  5. I had an idea to connect the "locked" signal of my main clock PLL to the asynchronous reset signal. In this way, at startup, before "locked" arrives, the registers will be reset as well as any time. What could go potentially wrong with such a design?
    For many years, we have successfully use the "locked" output of the PLL/MMCM to trigger our dedicated-HDL that resets the design.  Please see the post that I referenced above and also read the EETIMES article referenced in that post.

Cheers,
Mark

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