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Visitor
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Registered: ‎06-15-2017

Reset sequencing for IDELAYCTRL and IDELAYE3 is contradictory in UG571

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In UG571 (v1.6):

  • IDELAYCTRL section (p189/190) says the reset for IDELAYCTRL and IDELAYE3 should be applied together and released together.
  • IDELAYE3 section (p167) says the reset for IDELAYE3 should not be asserted until after IDELAYCTRL.RDY goes high.

Which of these is correct?

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Community Manager
Community Manager
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Registered: ‎08-08-2007

The IDELAYCTRL calibrates when its Reset is released. so the sequence "Release Reset" that you should follow:

From UG571: 

Release Reset
1. Hold all the EN_VTCs High for all of the used ISERDES and OSERDES.
2. Use the following sequence to bring the I/O out of reset:
a. Release the reset of the PLL/MMCM generating the clocks for the interface.
b. Wait for the PLL/MMCM to reach the LOCKED state.
c. Wait at least 50 application clock cycles (PLL/MMCM specification).
d. Release the reset of following primitives: IDELAYCTRL, IDELAY, ISERDES, OSERDES,
e. Wait until the RDY of all the used IDELAYCTRL primitives are asserted High.

 

Once the IDELAYCTRL and IDELAY resets are released at the same time calibration will complete. 

Thanks,
Sandy

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Community Manager
Community Manager
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Registered: ‎08-08-2007

There is a difference to previous families that if you hold the IDELAY reset high while the IDELAYCTRL is high then the IDELAYCTRL will not be able to calibrate properly. In 7 Series it was a normal follow for the user to release the reset of the IDELAYCTRL wait for RDY and then release the IDELAY reset. That is changed for UltraScale. They are both correct, what the table on p167 says is

 

The RST pin (reset) is synchronous with the CLK. When the IDELAYE3 is reset, the delay is set to the value defined by the DELAY_VALUE attribute. The reset of the IDELAYE3 should not be asserted until after the initial reset release sequence and
IDELAYCTRL.RDY goes High.

 

So the initial reset sequence says : 

d. Release the reset of following primitives: IDELAYCTRL, IDELAY, ISERDES, OSERDES,
e. Wait until the RDY of all the used IDELAYCTRL primitives are asserted High.
Now the application in the FPGA logic can be released after a delay of at least 64 clock cycles.

 

After this is done the user can reset the IDELAYE3 again while the design is running to value in the DELAY_VALUE. 

Does that make sense?

Thanks,
Sandy

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Visitor
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Registered: ‎06-15-2017

Thanks.

I think the statement at the end of p189 is misleading "3. Apply Reset to IDELAYCTRL, IDELAY, ISERDES, OSERDES, and ODELAY". From your answer this will have resets for both IDELAY and IDELAYCONTROL high at the same time then it will not calibrate properly.

I will therefore do the following at power up:

  1. Reset clock management tile and wait for 'locked' signal
  2. Then reset IDELAYCTRLE3 and wait for IDELAYCTRL.RDY to go high
  3. Then reset IDELAYE3 and ISERDESE3
  4. Then reset the application logic

Can you confirm this is all correct? Many thanks.

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Community Manager
Community Manager
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Registered: ‎08-08-2007

The IDELAYCTRL calibrates when its Reset is released. so the sequence "Release Reset" that you should follow:

From UG571: 

Release Reset
1. Hold all the EN_VTCs High for all of the used ISERDES and OSERDES.
2. Use the following sequence to bring the I/O out of reset:
a. Release the reset of the PLL/MMCM generating the clocks for the interface.
b. Wait for the PLL/MMCM to reach the LOCKED state.
c. Wait at least 50 application clock cycles (PLL/MMCM specification).
d. Release the reset of following primitives: IDELAYCTRL, IDELAY, ISERDES, OSERDES,
e. Wait until the RDY of all the used IDELAYCTRL primitives are asserted High.

 

Once the IDELAYCTRL and IDELAY resets are released at the same time calibration will complete. 

Thanks,
Sandy

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