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Voyager
Voyager
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Registered: ‎04-12-2012

Resetting of DSP48 registers

Hello,

Can the accumulator register inside a DSP48 be reset (using logic external to the DSP48) ?

I want to infer a multiply - accumulate circuit using HDL.

The acuumulator (obviously) needs to be reset on occasions...but I couldn't find in the datasheet whether it supports a reset.

https://www.xilinx.com/support/documentation/user_guides/ug579-ultrascale-dsp.pdf

My worry is that if the native DSP48 register doesn't support reset it'll use a general purpose register from the fabric with a performance penalty.

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2 Replies
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438 Views
Registered: ‎01-22-2015

@shaikon 

An option is to use the Xilinx Multiply Adder(MADD) v3.0  IP (ref document PG192).  The SCLR input to this IP allows you to reset all registers in the core.  Performance and resource utilization for the MADD is given <here> and shows that sometimes only a single DSP is used by the core (and no LUTs, FFs, or BRAM).  Fmax is often above 500MHz.

Mark

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Registered: ‎01-22-2015

@shaikon 

Oops - I am just seeing that you asked about Multiply-Accumulate (MACC) and not Multiply-Add (MADD).

For MACC, use the IP called DSP48 Macro v3.0 (ref document PG148).  During customization of this IP with the wizard, specify that instruction-0=A*B, instruction-1=P+A*B, and indicate that you want the Control Port called SCLR.  In your HDL, you can assert SCLR to clear all registers in the core.

Performance and Resource Utilization for the DSP48 Macro v3.0 is found <here>.

Mark