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Contributor
Contributor
5,888 Views
Registered: ‎10-22-2015

SLR Crossing and Laguna Registers

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Vivado : 2016.3
FPGA  : xcvu190

Hello,

I'm having a difficult time resolving timing violations when crossing an SLR boundary. My design is based on aggregating and broadcasting packets from x7 100G Aurora endpoints (402.8MHz @ 256-bit), where x5 endpoints are located on SLR2 (top) and x2 endpoints are located on SLR1. The design is fairly straightforward and leverage's Xilinx's AXI4-Stream IP, and I've isolated all problematic inter-SLR paths to be between AXIS Register Slices using floorplanning (i.e. pblocks). The problematic inter-SLR paths are a subset of the x2 RX and TX AXIS buses, since I'm using x2 full-duplex endpoints on SLR1. I've tried numerous implementation strategies and additional pblocks, but meeting timing is challenging due to the level of congestion.

After reading "UltraScale Architecture Configurable Logic Block," I suspect that this can be resolved by using Laguna cells, but when assigning Laguna cells to a pblock, they are never utilized. For example, I define a narrow symmetric & vertical pblock spanning SLR2 and SLR1, and only include Laguna and slice resources. I then assign the relevant problematic paths to the pblock. When doing this, my Laguna utilization is always zero. It seems the only way to utilize a Laguna resource is to manually move registers using floorplanning. This wouldn't be a problem if the first logic cell in each SLR region was a register, but I'm generally seeing a CLB cell between the register paths: REG (SL2) -> CLB (SL1) -> REG (SL1).

I hope this was clear. In summary, I'm looking for an approach on how to use Laguna registers when interconnecting two AXIS Register Slices between SLR regions.

Thanks!

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Xilinx Employee
Xilinx Employee
9,214 Views
Registered: ‎11-03-2016

First step, upgrade to 2016.4.

Now marketing might not like me for saying that out in the forums, but while the laguna sound like a smart idea, you are forgetting the tools here are fighting the hold time violations. TLDR, there is little hope in using those registers.

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Xilinx Employee
Xilinx Employee
9,215 Views
Registered: ‎11-03-2016

First step, upgrade to 2016.4.

Now marketing might not like me for saying that out in the forums, but while the laguna sound like a smart idea, you are forgetting the tools here are fighting the hold time violations. TLDR, there is little hope in using those registers.

View solution in original post

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Participant
Participant
3,428 Views
Registered: ‎08-28-2009

In Vivado 2018.1 it has become possible to constrain LAGUNA SLL TX and RX flip-flop pairs to Laguna sites without hold time issues.

As noted here: [https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug973-vivado-release-notes-install-license.pdf]

"It is now possible to use Laguna TX_REG registers to directly drive RX_REG registers for UltraScale+ devices only but not UltraScale. Prior to 2018.1 this was not permitted due to possibility of un-fixable hold violations but the router now has the ability to adjust clock delays on Laguna registers."

 

Whereas in 2017.4, this would be an error, in 2018.1, it seems to work. This should make it easier to reach timing closure for very high clock frequency designs that must cross the inter-SLR trenches.