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dharpeer
Adventurer
Adventurer
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Registered: ‎11-24-2020

SRL in Ultrascale+/Ultrascale

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Hi,

A LUT6 in SLICEM can only be used as a 32 bit and not a 64bit Shift register. As I read this is due to the master/slave operation. However, I don't understand how this works. Can anybody please explain.

 

Thanks

 

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avrumw
Expert
Expert
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Registered: ‎01-23-2009

A LUT6 in SLICEM can only be used as a 32 bit and not a 64bit Shift register. As I read this is due to the master/slave operation. However, I don't understand how this works. Can anybody please explain.

Not really. This has to do with the internal architecture of the LUT and Xilinx has not discussed the reason why in any documentation. It may be discussed in a Xilinx patent, but I haven't gone looking for it.

The only thing that is important for the user is the fact that this is the case - a LUT6 can implement a 32 but SRL.

If I had to speculate, I would guess that it is because the SRL functionality comes "for free-ish" due to reusing the mechanism that gets the configuration bits into the LUTs, which is known to be serial. My suspicion is that the configuration shift is done with Master/Slave pairs with two phase non-overlapping internal clocks - this accomplishes the shift with fewer transistors. But when acting as an SRL we don't have two phase non-overlapping clocks, so we are restricted to using every other element in the chain. But again, this is all speculation - the only thing that matters is that it is what it is (a 32 bit shift register).

Avrum

 

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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @dharpeer 

 

Have you looked at the CLB UG574: https://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf

 

sandrao_0-1611067447723.png

 

Thanks,

Sandy


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avrumw
Expert
Expert
526 Views
Registered: ‎01-23-2009

A LUT6 in SLICEM can only be used as a 32 bit and not a 64bit Shift register. As I read this is due to the master/slave operation. However, I don't understand how this works. Can anybody please explain.

Not really. This has to do with the internal architecture of the LUT and Xilinx has not discussed the reason why in any documentation. It may be discussed in a Xilinx patent, but I haven't gone looking for it.

The only thing that is important for the user is the fact that this is the case - a LUT6 can implement a 32 but SRL.

If I had to speculate, I would guess that it is because the SRL functionality comes "for free-ish" due to reusing the mechanism that gets the configuration bits into the LUTs, which is known to be serial. My suspicion is that the configuration shift is done with Master/Slave pairs with two phase non-overlapping internal clocks - this accomplishes the shift with fewer transistors. But when acting as an SRL we don't have two phase non-overlapping clocks, so we are restricted to using every other element in the chain. But again, this is all speculation - the only thing that matters is that it is what it is (a 32 bit shift register).

Avrum

 

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