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Visitor
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Registered: ‎11-28-2013

SUB_LVDS input common mode voltage

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For Zynq Ultrascale+ DS925 / table 17 states a minimum input common mode voltage of 0.5V for SUB_LVDS. According to XAPP894 this voltage can drop to 100mV for 7series when using LVDS standard and external 100 Ohm termination resistors. Is this also valid for Ultrascale+ architecture and SUB_LVDS?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @gloacker 

MIPI_DPHY_DCI recommended VCCO is 1.2V for input and output. MIPI_DPHY_DCI usage with VCCO = 1.5V is not recommended.

So, you can use XAPP894 solutions in your use cases. LVDS and LVDS_25 specifications are same between 7 Series and UltraScale+ FPGA's. Check device datasheet for more details. So, in case of Compatible Solution (resistor based circuit solution) same statement is applicable for UltraScale+ series FPGA as well " For SLVS transmitter: When using external termination resistors, the common mode voltage can drop to 100 mV."

To make sure you can always perform IBIS simulation for your IO setup and verify.

I am aware VCCO cannot be changed in IBIS simulation but it does not matter details are as follows: Check https://www.xilinx.com/support/answers/43989.html prior to going through content provided below.
As compatible solution uses external termination you can use same circuit with non-supported VCCO (in your case VCCO=1.5V). LVDS is actually VCCO independent IO standard. In Xilinx FPGA it become VCCO dependent because of internal termination and DC biasing feature. If it is not used it can be used with unsupported VCCO by LVDS_25 IO standard. This applicable for LVDS IO standard in HP bank as well.
Please check https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf (Page 131 end section: It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs))

Please note we have tested XAPP894 solutions with standard conditions that is at recommended VCCO provided by datasheet. So, PVT variation might affect worst case performance in your use case condition slightly. This note is applicable for both 7 series and UltraScale+ FPGA's. 

 

Regards,
Bhushan

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hello @gloacker 

Important thing to note here is XAPP894 is for Spartan-6 and 7 Series FPGAs which do not have I/O that can natively support D-PHY. While Zynq UltraScale+ MPSoCs supports MIPI DPHY IO. You can check more details on UG571.

Kindly check in UG471 Table 1-55:VCCO and VREF Requirements for Each Supported I/O Standard for IO standard list for 7 series and UG571. Table 1-77:VCCO and VREF Requirements for Each Supported I/O Standard for UltraScale+

XAPP894 also mentions on page 11 top section "The LVDS receiver in the FPGA can lower the common mode voltage to 300 mV when using the internal on-die termination resistors. When using external termination resistors, the common mode voltage can drop to 100 mV. "

Internal termination resistor (DIFF_TERM) in FPGA are 100ohms.

While external termination can be changed to get lower common mode voltage 100mV.

You can check example provided with XAPP894 simulated in Hyperlynx and SPICE and are tested in hardware with a D-PHY FMC development board https://www.xilinx.com/support/documentation/application_notes/xapp894.zip and Figure 11: FPGA Compatible D-PHY Receiver (uses 150ohms termination) for more detailed understanding. 

 

Regards,
Bhushan

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Visitor
Visitor
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Registered: ‎11-28-2013

Hi @bpatil 

thanks for explanation. I didn't mention that I cannot use native DPHY support because bank voltage is fixed to 1.5V in my case. That is why I am looking for an alternative standard (SUB_LVDS with external termination?) where XILINX can state a lower input common mode voltage down to 100mV also for Zynq Ultrascale+.

Or is there an option for a 1.5V powered bank to use the MIPI_DPHY_DCI_HS when it is configured as input only and only the high speed signal are used?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @gloacker 

MIPI_DPHY_DCI recommended VCCO is 1.2V for input and output. MIPI_DPHY_DCI usage with VCCO = 1.5V is not recommended.

So, you can use XAPP894 solutions in your use cases. LVDS and LVDS_25 specifications are same between 7 Series and UltraScale+ FPGA's. Check device datasheet for more details. So, in case of Compatible Solution (resistor based circuit solution) same statement is applicable for UltraScale+ series FPGA as well " For SLVS transmitter: When using external termination resistors, the common mode voltage can drop to 100 mV."

To make sure you can always perform IBIS simulation for your IO setup and verify.

I am aware VCCO cannot be changed in IBIS simulation but it does not matter details are as follows: Check https://www.xilinx.com/support/answers/43989.html prior to going through content provided below.
As compatible solution uses external termination you can use same circuit with non-supported VCCO (in your case VCCO=1.5V). LVDS is actually VCCO independent IO standard. In Xilinx FPGA it become VCCO dependent because of internal termination and DC biasing feature. If it is not used it can be used with unsupported VCCO by LVDS_25 IO standard. This applicable for LVDS IO standard in HP bank as well.
Please check https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf (Page 131 end section: It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs))

Please note we have tested XAPP894 solutions with standard conditions that is at recommended VCCO provided by datasheet. So, PVT variation might affect worst case performance in your use case condition slightly. This note is applicable for both 7 series and UltraScale+ FPGA's. 

 

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
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