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markheh
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Registered: ‎05-09-2018

SYSMON Event Mode No Conversion

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I am using the system management wizard configured in Event Mode (Continuous Sequencer Mode, No Channel Averaging, with reset_in and ADC Data Out enabled, and convst in). Calibration, Temp, VCCINT, VCCAUX, VCCBRAM, VREFP, VREPN, and vp/vn are enabled. My reference used by sysmon is internal.

I never see SYSMON complete a conversion (no eoc, no eos) with the configuration.

Upon release from reset, the sysmon is busy for 2807 DCLK. Once it isn't busy, I send a convst_in pulse synchronous with my 125 MHz DCLK. After another 484 DCLK, busy_out goes high for 30975 DCLK then low after.

Channel_out from the sysmon is initially 0 upon release of reset, but goes to 0x8 (calibration mode) after 5953 DCLK and stay 0x8.

However, when I change the timing mode from Event Mode to Continuous Mode, I see each channel conversions and the eoc/eos.

Why is my Event Mode not working properly? 

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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @markheh 

 

I build a testcase for a ZCU102 and I do not see the behaviour you describe.

I pulse the convst and I can see the busy assert / dessert and then the EOC pulse. 

Event_Mode.PNG

Then a second pulse and you can see the channel move on as expected

Event_Mode_2.PNG

I can send you on my very simple design its too large to attach, but I'll attach the XCI. 

 

Sandy

 

Thanks,

Sandy


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sandrao
Community Manager
Community Manager
741 Views
Registered: ‎08-08-2007

Hi @markheh 

 

I've used Event Mode a few times and have not seen this issue.

I made a quick testcase with the sequence you mentioned, what do you have the ADC Conversion Rate set to?

 

When I simulate I can see the Sysmon start on the Channel 8 Calibration. I dont see an EOC for Calibration channel but I do see the EOC for each subsequent Convst. 

SM_Sim.PNG

 

If you issue another Convst after the Busy deasserts do you see the channel change and the EOC pulse?

 

Sandy 

Thanks,

Sandy


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markheh
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Registered: ‎05-09-2018

Hi @sandrao,

 

With a DCLK of 125 MHz and ADC Conversion of 40 KSPS, the Clock Divider Value is 121, giving a ADC Clock Frequency of 1.03 MHz. This is on the ZCU102 eval board so there is no external channels, but it isn’t working on our board either where we enable multiple of the VAUX.

See attached for screenshot running in Event Mode and in Continuous Mode.

 

Some more details:

The DCLK to the sysmon is 125 MHz and the same clock used in my state machine to drive the convst_in.

Nothing ever happens after even with additional convst_in pulses generated with an VIO.

I've tried extending the convst_in pulse from 1 DCLK to several ADCCLK length wide incase the sysmon is missing it. I've tried delaying up to several seconds before sending the convst_in pulse to start the ADC conversion.

I've tried sending the convst_in before and after the calibration busy_out. I have DRP enabled in the core, but not using it and grounded the den, dwe, and din signals but this shouldn't matter either because the core works in the continuous mode. 

 

One thing I haven't tried is using convstclk instead of convst, but I'm not sure what is expected when using this signal.

 

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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @markheh 

 

In the 2nd grab, if I understand correctly you are in Continuous Mode so the signal Convst has no function.

The busy goes low around 68us and goes back high again, until around 100us. Its around this time that the conversions happen and the EOC pulses. 

I see this in simulation as well, that at the start that BUSY goes low and then high again without me requesting a conversion. 

Can you try to delay your Convst until after the second time that BUSY deasserts?

When I've used Event Mode it was with a VIO so when I would have issued the first Convst the SYSMON would have been sitting idle for a good amount of time.

 

Sandy

Thanks,

Sandy


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If starting with Versal take a look at our Versal Design Process Hub , Versal Blogs and the Versal Useful Resources .

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markheh
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Registered: ‎05-09-2018

Hi @sandrao,

I have tried previously delaying the Convst until after the second time that BUSY deasserts in the firmware. I also have an VIO that allows me to issue a convst at any time so I've waited seconds and even minutes real time before issuing the convst but this doesn't appear to make a difference. I've used it to issue multiple convst but an ADC conversion never happens (no eoc).

Yes, you are correct in stating that in the Continuous Mode, convst does not matter. In fact, it is not hooked up for that build.

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sandrao
Community Manager
Community Manager
655 Views
Registered: ‎08-08-2007

Hi @markheh 

 

I build a testcase for a ZCU102 and I do not see the behaviour you describe.

I pulse the convst and I can see the busy assert / dessert and then the EOC pulse. 

Event_Mode.PNG

Then a second pulse and you can see the channel move on as expected

Event_Mode_2.PNG

I can send you on my very simple design its too large to attach, but I'll attach the XCI. 

 

Sandy

 

Thanks,

Sandy


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub , Versal Blogs and the Versal Useful Resources .

------------------------------------------------------------------------------------------------

View solution in original post

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