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polarbear
Visitor
Visitor
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Registered: ‎10-27-2020

SelectIO SSTL15 between VU440 and VU040

Hi experts,

My company recently bought a board with VU440 on it, and I have a board with VU040, I connected them by a short high speed cable, in both sides I'm using SelectIO IP, and the IO standard is SSTL15. 

According to Xilinx's documents, the highest speed available is 1.2Gbps, while for my case,

From VU440 to VU040, it only worked under 400Mbps, I started to get error since 600Mbps.

From VU040 to VU440, it always worked well, from 400Mbps to 1.2Gbps.

So my questions are:

1) Are there any difference between the selectio IP between VU440 and vu040?

2) I measured a sstl15 signal from VU440 to VU040, the signal is swing from about 500mV to 1000mV, while the lowest value is not zero?

3) Termination setting, from VU440 to VU040, I'm using RT-40 in  VU040, is there anything else I need to set?

Regards

Chris  

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klumsde
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Registered: ‎04-18-2011

Hi @polarbear

You don't say how you transmit this data, I presume it's source synchronous, what that means is you transmit the data and the clock together.

As you increase the data rate then you can't just statically capture this data at the receiver, you need a dynamic capture scheme to tune the sample point in the data window. 

Maybe tell us how you capture the data here... 

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polarbear
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Registered: ‎10-27-2020

Hi Klumsde,

Thanks for your comments.

Yes, you are right, it's source synchronous, no matter what's the data rate is, I will run link training at the very beginning, then I'll capture the data with the link training result.

What do you mean by "dynamic capture scheme"? Can you give me an example?

By the way, I checked SSTL15 spec recently, it looks like the signal swing between 500mV - 1000mV is still within the range, which is 750mV +-175mV.

Regards

Chris

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klumsde
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Registered: ‎04-18-2011

I just mean that you adjust the clock and data relationship so the data can be reliably captured. So some sort of link training as you mention.

Maybe explain your receive circuit and tell us more about the failure you see above 400mbps. Is the data completely corrupted or is it word alignment that isn't correct. 

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polarbear
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Registered: ‎10-27-2020

we found a few bugs, now for 1.2Gbps, some times the link can't be up, once the link is ready, VU040 can receive data with no error. 

1) what kind of termination should be set? now we are using RT-40 in VU440 (tx) and RT-60 in VU040 (rx), any suggestion?

2) the IO standard we are using now is POD12, according to Xilinx document we should set the reference voltage 0.85V, while we can get a better performance with a reference of 0.75V.

Regards

Chris

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klumsde
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Registered: ‎04-18-2011

RTT_XX is the split input termination. XX being the line impedance 

For the TX you shouldn't need to have this on. There is output drive tuning here. 

Possible values for OUTPUT_IMPEDANCE attributes
are RDRV_40_40, RDRV_48_48, RDRV_60_60, and RDRV_NONE_NONE.

2) the IO standard we are using now is POD12, according to Xilinx document we should set the reference voltage 0.85V, while we can get a better performance with a reference of 0.75V.

POD12 is dedicated for high speed memory interfaces. So It is not intended for board to board communications. Neither is SSTL for that matter. This will potentially present some issue for SI. Which I think you are starting to see the beginnings of.

 

 

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polarbear
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Registered: ‎10-27-2020

Sorry,I made a mistake, TX side is RDRV_40_40, which is the default value; RX side is RTT_60.

In order to support 1.2Gbps, we have to use POD12, meanwhile it looks like the tx reference is 0.85V, while the reference in RX side should be 0.75V, then we can get a little better performance.

Regards

Chris

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