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Observer ozajay_99
Registered: ‎08-22-2019

Simulation of IP example design of RF data Converter IP


I am following the steps for IP Example design which is specified in document PG-269. Can we perform direct Simulation for it?

If yes, when I am doing simulation, I am getting the following errors:

(1) At first I was getting these error but I changed the simulator to VIVADO SIMULATOR and then it was fine.

[USF-Questa-48] Failed to locate 'vsim.exe' executable in the shell environment 'PATH' variable. Please source the settings script included with the installation and retry this operation again.


(2) But now I am getting these error. Can anyone tell me why exactly I am getting error? Which Target language should I specify VHDL or VERILOG or MIXED ?

[XSIM 43-3138] "c:/Users/jay.oza/usp_rf_data_converter_0_ex/imports/demo_tb.sv" Line 989. Cross Language Hierarchical name(DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0_i.inst.rfdc_ex_usp_rf_data_converter_0_i_0_rf_wrapper_i.rx0_u_adc.VIN_I01_N) is not supported in this context.

Any help from you guys will be appreciated, please.


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