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bolzw
Participant
Participant
416 Views
Registered: ‎07-15-2019

Sub-optimal placement for a bufg, how can i force bufg placement ?

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Hi,
I need to connect a clock input (HD bank pin, HDGC type) to a PLL/MMCM.
I use vivado 2020.2, US+ ZU9EV.
I have added a bufg between pin and MMCM but implementation fails :
"[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.". (see attached error log)

I have tried to force bufg in same clock region as IO pin but I am not sure I understand how to link IO pins to IOB_XxYx to CLOCK_REGION_XxYx.
As I get:
- IO_BN_L5_HDGC_AD7_G13_P_IBUF_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X1Y216
- my_design/util_ds_buf_0/U0/USE_BUFG.GEN_BUFG[0].BUFG_U (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X1Y22

I have tried:
=> "set_property CLOCK_REGION X1Y216 [get_cells {design_top/util_ds_buf_0}]"
Same error.

Is it the correct command ? is there an alternative to "CLOCK_DEDICATED_ROUTE FALSE" ?


=> "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IO_BN_L5_HDGC_AD7_G13_P_IBUF_inst/O]"
Implementation passed with this command, but it not recommanded by Vivado itself.

Thanks for your help.

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drjohnsmith
Teacher
Teacher
392 Views
Registered: ‎07-09-2009

Why have you added a bufg ? is there not one already in the MMCM ?

   if so, you will be trying to cascade bufg , which is not possible without going across chip routes.

another reason could be that you have connected the clock to a none clock capable pin, 

I'd also suggest  take off all the constraints you have apart from pin placement, clock speed and IO types,

    only once you have a basic design, and no errors in placement, start looking at the other constraints

 such as cross clock , 

For a simple design, Id not expect you to be looking at clock regions,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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3 Replies
drjohnsmith
Teacher
Teacher
393 Views
Registered: ‎07-09-2009

Why have you added a bufg ? is there not one already in the MMCM ?

   if so, you will be trying to cascade bufg , which is not possible without going across chip routes.

another reason could be that you have connected the clock to a none clock capable pin, 

I'd also suggest  take off all the constraints you have apart from pin placement, clock speed and IO types,

    only once you have a basic design, and no errors in placement, start looking at the other constraints

 such as cross clock , 

For a simple design, Id not expect you to be looking at clock regions,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

362 Views
Registered: ‎01-22-2015

@bolzw 

Yes, this is a rather odd feature of the HD banks in US+ devices.  As described on page 10 of UG572(v1.10):

...clocks that are connected to an HDGC pin can only connect to MMCMs/PLLs through the BUFGCEs. To avoid a design rule check (DRC) error, set the property CLOCK_DEDICATED_ROUTE = FALSE.

So, route your clock input through a BUFGCE and to the MMCM.  Next, run synthesis and implementation.  Vivado will then suggest using the CLOCK_DEDICATED_ROUTE = FALSE  constraint   *and*   Vivado will give you the exact format of the constraint.  Copy this constraint into the .xdc file for your Vivado project.

Cheers,
Mark

bolzw
Participant
Participant
244 Views
Registered: ‎07-15-2019

Hi,

I added a bufg because implementation failed with this setting:

- "primitive = auto" and "clock source = single ended clock capable pin" (I use a "HDGC pin)

After reading your post, I removed external bufg and tried several combinations and found one working:

- "primitive = mmcm" and "clock source = global buffer" (I guess global buffer setting forces tool to add a bufg but it not well documented).

Implementation passed without additional constraint.

 

thanks for your help.