09-18-2019 09:17 AM - edited 09-18-2019 09:23 AM
I'm using the ZCU102 board (with the Zynq Ultrascale+) and am trying to figure out how to synchronize a clock---let's assume 100MHz---to a 1PPS (1Hz) reference signal. I've been told that a PLL or MMCM should be able to accomplish this, but haven't had any luck in figuring out how.
Here's a minimal working example of what I'm trying to accomplish:
In my design, I count intervals of time---let's assume 10ns increments, one per tick---using the clock and need the count to be accurate. The 1PPS reference signal is very accurate and precise, and I want to synchronize the clock to it in order to correct for any clock drift that may occur. If the clock drifts from the 1PPS signal, it should be adjusted to be back in sync with the 1PPS signal.
Here are the constraints of the problem:
I'd really appreciate any advice I can get on this!
Note: I was able to find one similar discussion here, but it wasn't at all fruitful.
09-18-2019 09:35 AM
You need a long integration time on the phase filter of an external PLL. The internal PLL will not be able to do this. One divides down the 100 MHz to 1 Hz, and you youthe 1 Hz reference input to the PLL phase detector. Loop stability, lock time, all become pretty important (critical). One can do the same thing using digital signal processing, and a numerically controlled oscillator along with a higher frequency clock. I used a 48 bit DDFS, with jitter filter as part of a solution I used to sync to a 1 PPS GPS signal.