11-27-2018 10:14 PM
Dear Forum (@klumsde):
We're considering multiple (>50) RFSoCs for an application where signals have to be sampled synchronously. Synchronously meaning that if I was to apply the identical signal to each RFSoC ADC (with the same phase!) then I need the data to be perfectly aligned. Can this be done with these chips? The amount of DS or ANs are absolutely overwhelming and I'm not sure where to find the exact information I need :D
In a first step we're trying to synchronise two EVAL boards in that manner. Is there a sync'ed reset input to the EVAL board that I'm not aware of to align the onboard clocks? I must be able to tell both devices WHEN exactly to record data. This pulse which I generate externally will be sync'ed to the SYSREF of course, but is this kind of "Reset input" available somewhere? I must be able to reset all the clock dividers synchronously.
The same will be needed for the DACs: In the second step I also want the DACs to generate signals synchronously (meaning that all 8 DACs must put out the same signal with the same phase and no time offset).
Do you consider this task doable?
Best Regards and thanks for any help!
11-28-2018 01:09 PM - edited 11-28-2018 01:11 PM
Synchronising tiles across multiple chips and indeed across boards is supported.
The sysref needs to be delay matched to all tiles.
We've demonstrated this to some customers using 2xzcu1275 boards and a 3rd zcu1254 board was used to provide the clocking and Sysref to both boards and it was not used for converters.
I think you will be somewhat limited when using two zcu111 boards.
As you point out you'd likely have to safe start both sets of RF PLLs on the board so the clocks and sysref signals were aligned across boards I don't know what the capability is here.
Let me take a look and ask around to see what can be done.
11-28-2018 10:29 PM
Dear @klumsde Keith,
thanks for your first thoughts on this! That sounds promising.
We have two ZCU111 Boards and our FPGA developers are still in the evaluation phase. Since I'm responsible for Clocking (generation, distribution, alignment ...) I'll dig deeper into the differences between the ZCU111 and ZCU1275 board's clocking architecture differences then.
In what way might we be limited with the ZCU111? Is it due to the chip itself or due to the clocking architecture of the board (like I said I must check out the differences first) ??
My first approach on generating and distributing a high performance clock + sync signal is using HMC7043 Analog Devices Chips - any experience/thoughts on this?
Thanks for your help! I'm really looking forward to hearing from you about what can be done!
01-07-2019 06:37 AM
02-06-2019 03:47 PM
02-06-2019 09:51 PM
We're also considering a large design that would require synchronising across many RFSOCs. I have read the documentation (PG269) which indicates that a divided copy of the sampling clock should come into the fabric, and be used to sample a copy of sysref (also coming into the fabric).
The point of these extra signals in the fabric appears to be to set the delay in the FIFOs for each ADC.
This introduces a number of complications to the system design. Is it possible to timestamp ADC samples coming out of the core with respect to sysref ? Since sysref can be used to trigger updates of e.g. the NOC, ADC samples must be timestamped with their relation to sysref internally within the core. If we could get that information out of the core then there would be no need to align the FIFO delays.