System Monitor: DRP interface timeout

[emacann]

Hi,

I'm developing part of a complex system that will include the Ultrascale System Monitor.

The System Monitor is interfaced internally using the Dynamic Reconfiguration Port to log temperature and various voltages using custom interfaces.

I've some questions regarding the DRP interface implemented in this component, in particular regarding read operations:

1) Is there a maximum number of clock cycles to wait for the assertion of DRDY?
2) In case of a timeout (i.e. the maximum number of clock cycles has been reached), is it correct to reset the DRP using the System Monitor 'RESET' port?

Thanks,

Emanuele

[klumsde · Accepted solution]

Hi Emanuele,

In this case you are asserting den for a read or den+dwe to do a write then 4 dclk cycles later drdy will assert.

I don't know if a reset it needed.
Simply because it can't time out. there is an arbitration on the register map between the drp/i2c and jtag.

The only time I've seen the drp interface not respond is if you accidentally set the clock divider that divides the dclk down to generate the ADCCLK to a value that gives you too slow an ADCCLK. In this case the ADC locks up and no drp transactions are possible