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Participant kumarmurugan
Participant
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Registered: ‎07-04-2017

Tap setting in SelectIO Interface Wizard

What is the meaning of tap setting here? There is no detailed explanation in the PG.

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Registered: ‎01-22-2015

Re: Tap setting in SelectIO Interface Wizard

@kumarmurugan 

The tap setting is how you control the time delay of the IDELAY or ODELAY blocks.

As shown in the datasheet for your 7-Series FPGA (eg. Table 29 of DS182), changing the tap value by 1 will change the time delay by a value equal to 1/(32 x 2 x FREF),  where FREF is the frequency of the reference clock that you send to the IDELAYCTRL or ODELAYCTRL primitive.

Please see UG471 for more information about IDELAY and ODELAY.

Mark