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zhiha
Visitor
Visitor
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Registered: ‎03-06-2021

The detail about the sysref_fpga clk and fpga_refclk of the zcu111 in ug1271

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Here is my problem:

I'm using the zcu111, now I cannot find the detail about the sysref_fpga clk and fpga_refclk in ug1271, so I cannot write the xdc for the clock source.

zhiha_0-1618457637022.png

zhiha_1-1618457735823.png

 

Thanks for your help!

Best wishes

Zhiha

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pthakare
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323 Views
Registered: ‎08-08-2017

Hi @zhiha 

These clocks come from LMK PLL on the board.

pthakare_0-1618458642511.png

 

The constraints associated with them are as follows

pthakare_1-1618458885165.png

 

The complete xdc file for zcu111 is available here

https://www.xilinx.com/products/boards-and-kits/zcu111.html#documentation'

 

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pthakare
Moderator
Moderator
324 Views
Registered: ‎08-08-2017

Hi @zhiha 

These clocks come from LMK PLL on the board.

pthakare_0-1618458642511.png

 

The constraints associated with them are as follows

pthakare_1-1618458885165.png

 

The complete xdc file for zcu111 is available here

https://www.xilinx.com/products/boards-and-kits/zcu111.html#documentation'

 

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Reply if you have any queries, give kudos and accept as solution
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zhiha
Visitor
Visitor
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Registered: ‎03-06-2021

Thanks for your help. My clock xdc is actually like what you say.

But I have got some critical warning like that, I don't know the reason, can you give me some suggestion to solve this.

zhiha_0-1618460105337.png

 

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klumsde
Moderator
Moderator
270 Views
Registered: ‎04-18-2011

these warnings look like they are coming from some XDC for an IP rather than the top level on that manages the IO locations

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pthakare
Moderator
Moderator
270 Views
Registered: ‎08-08-2017

Hi @zhiha 

This seems not to be related to RF clocking anymore.

Wondering if you can create new post (on implementation area) sharing your xdc to get the clarifcations around this warnings.

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