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shengdoushifeif
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Registered: ‎12-15-2020

The using questions of IDELAYE3 and IDELAYCTRL of UltraScale+ FPGA

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First of all, I want to share my understanding of idelay3 and idelayctrl in the reference ug571 document:

From the introduction of EN_VTC that is pin of IDELAYE3 primitive, we know that when IDELAYE3 is set to TIME mode and EN_VTC is set to high, IDELAYCTRL can calibrate the number of taps in IDELAYE3, so that the delay of IDELAYE3 is equal to the delay value indicated by the parameter DELAY_VALUE of IDELAYE3. This process realizes the compensation of VT. When EN_VTC is set low, IDELAYCTRL can't compensate VT of IDELAYE3, but at this time, the number of taps of IDELAYE3 can be updated and read out through CNTVALUEIN and CNTVALUEOUT pins.

From the introduction IDELAYCTRL primitive, we know that when IDELAYE3 is set to TIME mode, according to the required reset sequence, resetting IDELAYCTRL can compensate VT for IDELAYE3. Because of the EN_VTC pin of IDELAYE3 is set to high during reset.

Then there are my inferences and questions based on the above understanding:

1.  My inference is that VT will be compensated only when the reset sequence is executed, IDELAYCTRL and IDELAYE3 will compensate for VT. So, after the reset, if EN_VTC keep low, will IDELAYCTRL never compensate IDELAYE3 for VT?

2. For example, if the working environment temperature of my FPGA changes in a large range, then if I reset IDELAYCTRL and IDELAYE3 and implement VT calibration when the environment temperature is 0 ℃. After that, I don't reset IDELAYCTRL and IDELAYE3 again. When the environment temperature changes to 50 ℃, does IDELAYE3 's delay change with the same tap number?

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sandrao
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Registered: ‎08-08-2007

Hi @shengdoushifeif 

 

My question is about step 8. First the DELAY_VALUE is 500ps. After the reset sequence done, the number of taps in IDELAY is 100. If I follow the above procedure, updating the number of taps through the CNTVALUEIN pins, for example, 200taps corresponds to 1000ps. And after setting EN_VTC high in step 8, will IDELAYCTRL always automatically adjust the number of taps to ensure idelay delay is 1000ps?

Yes, exactly when you Load the new delay with the CNTVALUEIN and reassert the EN_VTC the VT will track to the new delay. So it will track to the 1000ps (not the original 500ps).

Thanks,

Sandy


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sandrao
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Registered: ‎08-08-2007

1.  My inference is that VT will be compensated only when the reset sequence is executed, IDELAYCTRL and IDELAYE3 will compensate for VT. So, after the reset, if EN_VTC keep low, will IDELAYCTRL never compensate IDELAYE3 for VT?

To be clear if you have EN_VTC high and do not apply the correct reset sequence the impact is that you may not get the correct delay as defined by DELAY_VALUE. 

You are correct that after the reset sequence if the EN_VTC is low then you will get the correct delay defined by DELAY_VALUE but it will not be compensated for VT.

2. For example, if the working environment temperature of my FPGA changes in a large range, then if I reset IDELAYCTRL and IDELAYE3 and implement VT calibration when the environment temperature is 0 ℃. After that, I don't reset IDELAYCTRL and IDELAYE3 again. When the environment temperature changes to 50 ℃, does IDELAYE3 's delay change with the same tap number?

Say you've DELAY_VALUE =100ps. When BISC runs at 0C it finds the tap size is 5ps, it will use 20 taps to give the required 100ps. Then the environment changes to 50C and the tap size is now 4.5ps then is takes 22 taps and BISC (IDELAYCTRL) will increase the number of taps to 22. You do not need to anything, once the IDELAY is TIME with EN_VTC high and the correct reset sequence IDELAYCTRL will automatically change the number of taps to give the requested DELAY_VALUE, it you monitor the CNTVALUEOUT when the device is running you can see the number of taps used change with VT.

Thanks,

Sandy


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shengdoushifeif
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Registered: ‎12-15-2020

Thank you for your reply!

I have another question. In UG571 page 192-193, it introduces a procedure in VAR_LOAD mode to update the number of taps. 

a1.PNGa2.PNG

My question is about step 8. First the DELAY_VALUE is 500ps. After the reset sequence done, the number of taps in IDELAY is 100. If I follow the above procedure, updating the number of taps through the CNTVALUEIN pins, for example, 200taps corresponds to 1000ps. And after setting EN_VTC high in step 8, will IDELAYCTRL always automatically adjust the number of taps to ensure idelay delay is 1000ps?

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sandrao
Community Manager
Community Manager
671 Views
Registered: ‎08-08-2007

Hi @shengdoushifeif 

 

My question is about step 8. First the DELAY_VALUE is 500ps. After the reset sequence done, the number of taps in IDELAY is 100. If I follow the above procedure, updating the number of taps through the CNTVALUEIN pins, for example, 200taps corresponds to 1000ps. And after setting EN_VTC high in step 8, will IDELAYCTRL always automatically adjust the number of taps to ensure idelay delay is 1000ps?

Yes, exactly when you Load the new delay with the CNTVALUEIN and reassert the EN_VTC the VT will track to the new delay. So it will track to the 1000ps (not the original 500ps).

Thanks,

Sandy


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub , Versal Blogs and the Versal Useful Resources .

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shengdoushifeif
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Registered: ‎12-15-2020

Thank you for your reply. Your reply perfectly answers my question. ^_^

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