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florian_
Observer
Observer
548 Views
Registered: ‎03-25-2013

Thermal Test Design

Hello everyone,

for the purpose of evaluating the thermal design of a custom board featuring an UltraScale, I aim to develop a design which uses as many of the FPGA's resources as possible. I'm going to use

set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]

as a safe guard. Anyone has recommendations on how to really max thermal dissipation without destroying the part?

Thanks,

 

Florian

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4 Replies
simon
Xilinx Employee
Xilinx Employee
503 Views
Registered: ‎08-25-2010

Hi @florian_ 

@you can use bufgce to enable or disable different resources, power down GT, control clock output frequencies etc.

Thanks
Simon
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u4223374
Advisor
Advisor
495 Views
Registered: ‎04-26-2015

@florian_ I think the tricks would be:

- Lots of small processing units that are largely independent but use all types of hardware (FFs, LUTs, DSPs, BRAM). Small, independent processing units will make place & route easier, which then leads into...

- Maximum clock speed rather than maximum logic (better to be 80% full at 400MHz than 90% full at 100MHz). Most of the heat is going to come from switching, so you want <resources> * <clock speed> as high as possible.

 

Similarly, turn on every register available in the DSPs and BRAMs. More registers = more switching, and it gets you more clock speed too.

 

gnarahar
Moderator
Moderator
470 Views
Registered: ‎07-23-2015

@florian_ 

@simon and @u4223374  provided good details on how you can try loading up your FPGA to get Max Power. 


for the purpose of evaluating the thermal design of a custom board featuring an UltraScale,


I am trying to understand your end goal or intent here. If you are evaluating the Thermal Design of the board, wouldn't doing a Thermal Simulation post calculating the Max Power @ Max Tj in XPE be a better and easier option to see if the Thermal Solution of the board can handle it?

It could also be a case of you having the board and want to study the Max Power the board can handle and want to go down the RTL path, but I wanted to understand the bigger picture and your end goal to see if we can suggest better solutions.  

- Giri
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florian_
Observer
Observer
443 Views
Registered: ‎03-25-2013

Thank you @simon and @u4223374 for your recommendations.

@gnarahar- the end goal is simply to validate the cooling solution works as required..

Thanks, Florian

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