UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor ksr203
Visitor
187 Views
Registered: ‎01-13-2019

UART in PL

 

 

Hi I'm using zcu102 board and I made a UART RTL code but It doesn't work well

 

I made block diagram like below and simulated it.

 

I wondered why it isn't work well and if the protocol of my UART code is right.

pic1.png

block_diagram.PNG

uart_result.png

0 Kudos
3 Replies
Scholar drjohnsmith
Scholar
179 Views
Registered: ‎07-09-2009

Re: UART in PL

You've made a UART or instantiated a standard free IP from Xilinx ?

My first guess from that terminal is the baud rate in the UART and the terminal do not agree.

Show us your code and we might be able to help more.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Visitor ksr203
Visitor
171 Views
Registered: ‎01-13-2019

Re: UART in PL

module uart_baud(clk, reset_n, T_clk);
  input clk, reset_n;
  output reg T_clk;

  /* insert your code */

  reg[8:0] counter;

  always@(posedge clk or negedge reset_n) begin
 if(!reset_n) begin
  counter <= 9'b0_0000_0000;
  T_clk <= 1'b0;
 end
 else begin
  if(counter == 9'b1_1011_0010) begin //1101_1001
   counter <= 9'b0_0000_0000;
   T_clk <= ~T_clk;
  end
  else begin
   counter <= counter + 1;
  end
 end
  end
 

endmodule
 

 

I thought zcu102's clock is 100MHz is it right?

 


module uart_trans(clk, resetn, T_clk, write_TDR, data_in, TxD, trans_done);
 
  input clk;
  input resetn, T_clk, write_TDR;
  input [7:0] data_in;
  output TxD;
  output trans_done;

  reg[9:0] TDR;
  reg[3:0] BitCnt;
  reg trans_done_Tclk;
  reg [1:0] state_Tclk;
  reg [1:0] state_clk;

  assign TxD = TDR[0];
  assign trans_done = (trans_done_Tclk == 1'b1 && state_clk == 1'b1) ? 1 : 0;
 
  always @ (posedge T_clk or negedge resetn)
  begin
 if (!resetn)
   begin
  state_Tclk <= 1'b0;
      TDR <= 10'b11_1111_1111;
  BitCnt <= 3'd0; 
      trans_done_Tclk <= 1'b0;
   end
 
 else begin
  case(state_Tclk)
      2'b00 :
  begin
   TDR <= {1'b1,data_in,1'b0};
   BitCnt<=0;
   state_Tclk <= 1;
   trans_done_Tclk <= 0;
  end
      
      2'b01 :
   if (BitCnt < 7) begin
    TDR <= {2'b11,TDR[8:1]};
    BitCnt<=BitCnt+1;
   end
   else begin
    TDR <= {2'b11,TDR[8:1]};
    BitCnt<=BitCnt+1;      
    state_Tclk <= 2'b10;
    trans_done_Tclk <= 1;
   end
  2'b10 : begin
    TDR <= 10'b11_1111_1111;
    state_Tclk <= 2'b00;
    BitCnt<=0;
   end
  endcase 
   end
  end 
 
  always @ (posedge clk or negedge resetn)
  begin
    if (resetn == 1'b0)
      begin
        state_clk <= 2'b00;
      end
    else
 case (state_clk)
        2'b00:
         begin
   /* insert your code */
   if(trans_done_Tclk) state_clk <= 1;
   else state_clk <= 0;
  end
        2'b01:
         begin
   /* insert your code */
   state_clk <= 2'b10;
  end
  2'b10 : if(state_Tclk==2'b01) state_clk <= 2'b00;
      endcase
 end
 
endmodule

 

0 Kudos
Scholar drjohnsmith
Scholar
134 Views
Registered: ‎07-09-2009

Re: UART in PL

and the simulation of your uart ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos