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Visitor lsisaxon
Visitor
1,206 Views
Registered: ‎03-06-2018

UG583 XCZU3EG

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Hi,

 

I refer to page 172 of the UG583 v1.12.1.

PS Reset (External System Reset and POR Reset)
•Connect PS_SRST_B to a 4.7 kΩ pull-up resistor to VCCO_MIO0 near the Zynq UltraScale+ MPSoC.
•Connect PS_POR_B to a 4.7 kΩ pull-up resistor to VCCO_MIO0 near the Zynq UltraScale+ MPSoC.

 

Question, what is VCCO_MIO0? Is it VCCO_PSIO3 or is it something else?

 

In the change version 1.11 dated 02/22/2018, it was mentioned,

"In PS Reset (External System Reset and POR Reset), replaced VCCO_PSIO[3] with VCCO_MIO0 in first bullet, and added two new bullets."

 

Question, what is the reason for the change, I cannot find VCCO_MIO0 referenced anywhere else except in the above sections. Can I safely presume that it actually means VCCO_PSIO3?

 

Thank you.

 

Best regards,
Saxon

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Moderator
Moderator
1,547 Views
Registered: ‎09-18-2014

Re: UG583 XCZU3EG

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Isisaxon,

 

Yes, that looks like a typo to me. It should read "VCCO_PSIO[3]" not "VCCO_MIO0". I am guessing the previous change was made with old Zynq SOC PS config rail syntax in mind. I will follow up with our documentation team to file a change request to address this issue asap with the next UG583 revision. 

 

Regards,

T

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Moderator
Moderator
1,548 Views
Registered: ‎09-18-2014

Re: UG583 XCZU3EG

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Isisaxon,

 

Yes, that looks like a typo to me. It should read "VCCO_PSIO[3]" not "VCCO_MIO0". I am guessing the previous change was made with old Zynq SOC PS config rail syntax in mind. I will follow up with our documentation team to file a change request to address this issue asap with the next UG583 revision. 

 

Regards,

T

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Visitor lsisaxon
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Registered: ‎03-06-2018

Re: UG583 XCZU3EG

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Thank you very much! :)

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Observer luckzzylb
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Registered: ‎08-14-2017

Re: UG583 XCZU3EG

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Hi, tenzinc,

I found in the newest change version 1.13 dated 08/15/2018 of UG583, page 177:

 

PS Reset (External System Reset and POR Reset) 


•Connect PS_SRST_B to a 4.7 kΩ pull-up resistor to VCCO_PSIO[0] near the
Zynq UltraScale+ MPSoC.


• Connect PS_POR_B to a 4.7 kΩ pull-up resistor to VCCO_PSIO[0] near the
Zynq UltraScale+ MPSoC. 

 

Why it is changed to VCCO_PSIO[0]?

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