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drjohnsmith
Teacher
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Registered: ‎07-09-2009

Ultra scale JTAG TDO pin, is it Open collector ?

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I look at the TDO pin of the FPGA with a scope whilst using the sysmon to measure temperature,

 

FPGA is un configured.

 

most of the time, TDO look's like a nice square edged waveform,

     

but

   

Every second or so, I see a slow rising edge, as one would have with an Open collector , with a rise time of the order of 1 us.

 

Checked other pins, and all good square edges, checked psu, all good.

 

 

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sandrao
Community Manager
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Registered: ‎08-08-2007

Looking at UG570 Table 6-1: TAP Controller Pins it says :
TDO Out Pull-up Test Data Out - TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device. TDO is an active driver output. TDO has an internal resistive pull-up to provide a logic High if the pin is not active.

Thanks,

Sandy


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sandrao
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Registered: ‎08-08-2007

Looking at UG570 Table 6-1: TAP Controller Pins it says :
TDO Out Pull-up Test Data Out - TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device. TDO is an active driver output. TDO has an internal resistive pull-up to provide a logic High if the pin is not active.

Thanks,

Sandy


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michael.n.eller
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Registered: ‎08-20-2018

UG570 has a note in the revision history for revision 1.11

"Removed TDO from JTAG"

I assume this is referring to the removal of the recommendation to have a 4.7K pull-up on TDO? What was the reasoning behind this change? Is it only because the internal pull-up was deemed sufficient enough or is there another reason that Xilinx modified their suggestion to have a pull-up on TDO?

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michael.n.eller
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Registered: ‎08-20-2018

@michael.n.eller wrote:

UG570 has a note in the revision history for revision 1.11

"Removed TDO from JTAG"

I assume this is referring to the removal of the recommendation to have a 4.7K pull-up on TDO? What was the reasoning behind this change? Is it only because the internal pull-up was deemed sufficient enough or is there another reason that Xilinx modified their suggestion to have a pull-up on TDO?


This was in UG583 actually, not UG570.

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drjohnsmith
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Registered: ‎07-09-2009

As a matter of practice,

  I'd always put a pull up resistor on all the JTAG pins,

         If you have TDI conected to the previous TDO , then only one resistro is normal,

          but it does make debugging much easier to have even a  0201 resisotr to probe.

 

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drjohnsmith
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Registered: ‎07-09-2009

@sandrao 

What sort of value is the internal pull up on the TDO pin

 

I understood it was of order 50 K , hence the slow rise seen on the trace provided.

I'd always put an external resistor on TDO,

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sandrao
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Registered: ‎08-08-2007

Hi @drjohnsmith 

 

The pullup on TDO should be in the same range as the regular IO. So say Bank 0 is powered at 3.3V the Irpu = 175uA, giving a R of ~19kohm, 

 DS.PNG

Thanks,

Sandy


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drjohnsmith
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Registered: ‎07-09-2009

Yep, thats th elowest value of internal resistance,

  but it could be 44 K ohm if its at the low end of current at 3v3,

or 120 K if you rusing the 1v2 IO standard,

 

QED. I always put an external resistor on the TDO / TDI line,   not least it alows debugging.

 

  

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