09-03-2015 04:49 PM
In Table 2-1 of pg047-gig-eth-pcs-pma.pdf, it says that UltraScale supports "Synchronous LVDS SelectIO" but doesn't support "Asynchronous LVDS SelectIO". Is Xilinx planning on adding "Asynchronous LVDS SelectIO" support for this IP core in the future revision release?
05-11-2017 09:51 AM
Solved in Vivado 2017.1 (refer to Table 2-1 in pg047-gig-eth-pcs-pma.pdf)
05-11-2017 09:51 AM
Solved in Vivado 2017.1 (refer to Table 2-1 in pg047-gig-eth-pcs-pma.pdf)