02-13-2020 07:48 AM
Hi to all,
I have a project to connect a CameraLink interface camera to ZCU102 evaluation board. For that, I implemented my deserialization component completely based on the XAPP1315. However, I got an error as bellow during implementation, which suggests adding a BUFG between IBUFDS_DIFF_OUT and MMCM.
ERROR: [Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM
According to AR# 62868 , the reason seems to be the existence of another MMCM in the same clock region. Actually, I have two CameraLink channels (Medium) each channel by one LVDS clock and 4 LVDS data which are all located in same bank. Based on this, I have instantiated two MMCMs in the same bank unavoidably.
However, I added a BUFG between the MMCM and IBUFDS_DIFF_OUT but still, I got the following error:
[DRC REQP-1945] IDELAYE3.IDATAIN connected to other loads check: The IDELAYE3 cell IDELAYE3_inst pin IDELAYE3_inst/IDATAIN attached to net clk_IBUF is also connected to other loads. This is not routable due to conflicting attributes for the net.
I read this AR# 69367 and added the corresponding constraint to ignore the DRC error, and now I am getting another error as bellow:
[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
Can anybody explain the situation?
Thank you very much in advance.
02-13-2020 08:09 AM
02-14-2020 07:24 AM
Thank you for your reply. I read the user guide.
As I wrote, I have connected the two CameraLink channels (each by one LVDS clock and four LVDS data lines) to one bank (bank number 66). For that, two MMCMs should be instantiated (each for one channel) which is not possible in UltraScale+ since there are only one MMCM and two PLLs in each CMT. I tried to use PLL instead of MMCM but the problem is that when I am using PLL, I am getting the following message:
[Place 30-899] Unroutable Placement - The Input buffer driving a PLL clock input needs to be in the same clock region as the PLL or driving an appropriate Clock buffer for the PLL clock input. If the I/O is locked to HIGH_DENSITY IO banks, please review and update the LOC constraints or insert a BUFGCE instance in between as I/O driving PLL can not be placed in HIGH_DENSITY IO banks. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
I have checked the IO pins, but I could not find any issues.