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wenhaohuang
Participant
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Registered: ‎02-10-2017

UltraScale+ HDMI: untrouted net?

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There is a problem  when I build the HDMI project for the ZCU102 board. After implemention there is a critical warning like:[Route 35-54] Net: design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/gtrefclk0_in[0] is not completely routed.


Is there any solution for this problem?

360截图20171108185028182.jpg

360截图20171108185935238.jpg360截图20171108190036214.jpg

 

 

best regards,

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florentw
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Registered: ‎11-09-2015

Hi @wenhaohuang,

 

There is an example design for HDMI on the ZCU102 in vivado 2017.3. I think you might want to have a look. This could be a good starting point.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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syedz
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2,202 Views
Registered: ‎01-16-2013

@wenhaohuang,

 

Can you show us the schematic of the unrouted net? Is it possible to share the post opt dcp file to debug this issue?

Check the following Answer record on debugging unrouted nets:

https://www.xilinx.com/support/answers/53854.html

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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wenhaohuang
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2,193 Views
Registered: ‎02-10-2017

The schematic of the unrouted net like this below?

 

360截图20171108193452151.jpg

360截图20171108195153846.jpg

360截图20171108201447998.jpg

360截图20171108201529654.jpg

 

 

 

And  opt.dcp in the attachement.Thanks for your reply!

 

 

 

 

 

 

 

 

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syedz
Moderator
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2,178 Views
Registered: ‎01-16-2013

@wenhaohuang,

 

From the error message, the connection of GT in single quad doesn't seem to be correct. Please check Figure 2-8 at page number 36 in below UG :

https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf#page=36

 

Also check this Answer record: https://www.xilinx.com/support/answers/66823.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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florentw
Moderator
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3,067 Views
Registered: ‎11-09-2015

Hi @wenhaohuang,

 

There is an example design for HDMI on the ZCU102 in vivado 2017.3. I think you might want to have a look. This could be a good starting point.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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wenhaohuang
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2,158 Views
Registered: ‎02-10-2017

 Yes, there is a example.I used the vivado 2017.3 to open the example,but it didn't work .Just now I try again and it works. Thank you very much ! 

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florentw
Moderator
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2,137 Views
Registered: ‎11-09-2015

Hi @wenhaohuang,

 

As the issue is solved could you close the thread by marking a response as solution?

 

Thanks and Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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wenhaohuang
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2,118 Views
Registered: ‎02-10-2017

Hi @florentw

Sorry,I  don't know  how to close the thread.Do you mean that set your response as solution ? And thank you again for your help.

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florentw
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2,116 Views
Registered: ‎11-09-2015

Hi @wenhaohuang,

 

Yes set a response as solution. Thanks for doing it.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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randriantsoa
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Registered: ‎06-13-2019

Hi,

 

I got the same errors when I tried to move the zcu102_hdmi_8b_exdes_2018_3 to zcu104 board with the appropriate xdc file (pinning modified for matching with zcu104 board).

[DRC RTSTAT-1] Unrouted nets: 2 net(s) are unrouted. The problem bus(es) and/or net(s) are hdmi_example_zcu102_i/vid_phy_controller/inst/gt_usrclk_source_inst/gtrefclk0_in[0], and hdmi_example_zcu102_i/vid_phy_controller/inst/gt_usrclk_source_inst/gtrefclk1_in[0].

I use Vivado 2018.3.

Could you help me?

 

Best regards,

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florentw
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Moderator
590 Views
Registered: ‎11-09-2015

Hi @randriantsoa 

Our Community Help has a tip that might help you : Tip: If the message is older than 6-12 months, please post a new message rather than adding to the existing thread. Your inquiry will have a better chance of being picked up by an expert if it is a new topic.

 

https://forums.xilinx.com/t5/help/faqpage/faq-category-id/posting#posting

 

I would suggest you create a new topic on the appropriate board


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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