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Observer kevinclaycomb
Registered: ‎12-19-2012

Ultrascale+ BUFGCE_DIV CLR

We are migrating a design from a Zynq 7000 to the Zynq Ultrascale+ that uses a source sync center aligned DDR LVDS interface from an ADC to capture data.  The ADC provides one data lane, a bit clock, and a frame clock.  On the Ultrascale+ we are just using a component architecture with idelay and iserdes since it more easily migrates from our 7 series design.  Upon power up the ADC will be running at a default clock rate and then once we configure it after boot it will generate the appropriate rates for our application.  At the moment we are pulsing the CLR on the BUFGCE_DIV after configuration, along with the ISERDES resets.  The signal hitting the CLR is run through a synchronizer from another clock domain to the bit clock domain that is the input to the BUDGCE_DIV.  This synchronizer can cause timing errors if it gets placed too far away. 



1. Is there really any reason to hit the CLR on the BUFGCE_DIV?  Will it handle the clock rate change on the input just fine without the clear?  We will still reset the iserdes so a momentary glitch shouldn't matter.

2.  The documentation says that the CLR is an asynchronous reset assertion.  That seems to imply that internally the counter will stop asynchronous to the output DIV clock.  Does it also imply that the CLR pin can be used async to the input clock?  e.g. we don't really need to synchronize it.





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Community Manager
Community Manager
Registered: ‎08-08-2007

Re: Ultrascale+ BUFGCE_DIV CLR

Hi @kevinclaycomb


An AR that might be of interest : https://www.xilinx.com/support/answers/67885.html

You are using an ADC so there is no ISERDES skew requirement but its recommended to use the same setup as recommended for the OSERDES. The CLR is a good idea to ensure that the divided clocks are all aligned. 

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