cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
fabio_malatesta
Visitor
Visitor
835 Views
Registered: ‎08-03-2020

Ultrascale Block RAM ECC

Jump to solution

The documentation for the Ultrascale devices states that with RAM ECC enabled "Simultaneous decoding and encoding of the same read/write address is not allowed". We want to be able to perform simultaneous read/write operations to the same address and can handle it so that we discard the read data at the collision. My question is:

During the case with simultaneous decoding and encoding of the same read/write address we understand that we can get an ECC error and that the read data may be invalid. Will the write operation of checksum and data still always be successful?

In case the write operation will not be successful then we can handle that by masking the read enable signal but we would like to avoid that since it can affect the maximum frequency we are able to attain.

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
pthakare
Moderator
Moderator
763 Views
Registered: ‎08-08-2017

Hi @fabio_malatesta 

ill the write operation of checksum and data still always be successful?

This is made on Write_mode for both the ports. As you know ,Collision occurs when both ports are accessing the same address. In this condition

       •When both ports are reading, the operations complete successfully.

  • When both ports are writing different data, the memory location is written with non-deterministic data.
  • When one port is writing and the other port is reading, the write is always successful but the resulting read memory value can vary (Tables below)

 

In the below tables it specifies the “Resulting data out portA” , “Resulting Data out Port B” and “Resulting memory value “ when there is address collision in Synchronous (common) or Asynchronous (Independent clocking )

 

pthakare_0-1596624544988.jpeg

 

 

Below are the IP perspective collision check methods.

 

There are types of collision and certain guidelines to follow which are documented in IP product guide on page 50 for both synchronous and asynchronous clocks.

https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_4/pg058-blk-mem-gen.pdf

 

to detect the collision in Structural (post synthesis or implementation ) or in behavioral simulation we have the below options in block memory generator IP

 

pthakare_1-1596624545057.jpeg

 

 

For the options of ALL, WARNING_ONLY and GENERATE_X_ONLY, the collision detection feature is enabled in the UNISIM models to handle collision under any condition.

The NONE selection is intended for designs that have no collisions and clocks (Port A and Port B) that are never in phase or within 3000 ps in skew.

If NONE is selected, the collision detection feature is disabled in the models, and the behavior during collisions is left for the simulator to handle.

So, the output will be unpredictable if the clocks are in phase or from the same clock source or within 3000 ps in skew, and the addresses are the same for both ports.

The option NONE is intended for design with clocks never in phase.

 

In behavioral Simulation model options , selecting the “Disable collision warnings”  disables the warning message during the behavioral simulation.

 

Now coming to possible solution

 

Make sure that you are following the above guidelines

 

•When both ports are reading, the operations complete successfully  -> Warnings can be safely ignored

  • When both ports are writing different data, the memory location is written with non-deterministic data. ->  Need to avoid this condition in design .
  • When one port is writing and the other port is reading, the write is always successful but the resulting read memory value can vary (Tables below) -> Check if read memory value is as per requirement , if not change the WRITE_MODE as per requirement.
-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

1 Reply
pthakare
Moderator
Moderator
764 Views
Registered: ‎08-08-2017

Hi @fabio_malatesta 

ill the write operation of checksum and data still always be successful?

This is made on Write_mode for both the ports. As you know ,Collision occurs when both ports are accessing the same address. In this condition

       •When both ports are reading, the operations complete successfully.

  • When both ports are writing different data, the memory location is written with non-deterministic data.
  • When one port is writing and the other port is reading, the write is always successful but the resulting read memory value can vary (Tables below)

 

In the below tables it specifies the “Resulting data out portA” , “Resulting Data out Port B” and “Resulting memory value “ when there is address collision in Synchronous (common) or Asynchronous (Independent clocking )

 

pthakare_0-1596624544988.jpeg

 

 

Below are the IP perspective collision check methods.

 

There are types of collision and certain guidelines to follow which are documented in IP product guide on page 50 for both synchronous and asynchronous clocks.

https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_4/pg058-blk-mem-gen.pdf

 

to detect the collision in Structural (post synthesis or implementation ) or in behavioral simulation we have the below options in block memory generator IP

 

pthakare_1-1596624545057.jpeg

 

 

For the options of ALL, WARNING_ONLY and GENERATE_X_ONLY, the collision detection feature is enabled in the UNISIM models to handle collision under any condition.

The NONE selection is intended for designs that have no collisions and clocks (Port A and Port B) that are never in phase or within 3000 ps in skew.

If NONE is selected, the collision detection feature is disabled in the models, and the behavior during collisions is left for the simulator to handle.

So, the output will be unpredictable if the clocks are in phase or from the same clock source or within 3000 ps in skew, and the addresses are the same for both ports.

The option NONE is intended for design with clocks never in phase.

 

In behavioral Simulation model options , selecting the “Disable collision warnings”  disables the warning message during the behavioral simulation.

 

Now coming to possible solution

 

Make sure that you are following the above guidelines

 

•When both ports are reading, the operations complete successfully  -> Warnings can be safely ignored

  • When both ports are writing different data, the memory location is written with non-deterministic data. ->  Need to avoid this condition in design .
  • When one port is writing and the other port is reading, the write is always successful but the resulting read memory value can vary (Tables below) -> Check if read memory value is as per requirement , if not change the WRITE_MODE as per requirement.
-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post