I've got some issue when running Vivado on Ultrascale FPGA:
INFO: [Route 35-325] The following overlapped node exist in the design and there is low overall congestion. 1. XIPHY_L_X157Y420/CLK_LEAF_MUX_XIPHY_8_CLK_LEAF Overlapping nets: 2 <instance_0>/clk_multiplier/clk_2x_i <instance_1>/clk_multiplier/clk_2x_i
I saw also warning that tool is not able to reach interconnect fabric with 5 hops for that net.
There are some changes causing that issue - few flops and muxes added.
How to overcome such issue - any tool build-in options ?
Or should I use BUFR to correct clock routing?
Vivado is not able to route that 1 net from few hundred thousands.
After some RTL changes - there is new meaningful error:
ERROR: [Place 30-912] Bank 66 has 7 different clocks driving IO loads in the bottom half. There can only be a maximum of 6 clocks in any half of an IO bank. The list of clock source instances driving IO loads in this half of the bank is as follows: