03-23-2019 05:27 AM
Hello everyone, I am developing a data acquisition system based on a zynq ultrascale+ board. While I didn't have any problem with the 7 series iserdese and oserdese I am having trouble implementing the iserdese3 ultrascale primitive. In particular after my framing fsm has locked the incoming pattern by bit slipping I should expect a simple 8 bit counter output. However each 7 counter beats the output is wrong more or less like this:
08 01 02 03 04 05 06 07 00 09 0a. Is it a bit slip problem or a timing issue? Thanks in advance
03-24-2019 11:01 PM
Can you please share the ILA screenshot depicting this behaviour ?
Did you implement the bitslip in logic?
03-25-2019 10:54 AM
Hi, unfortunately as soon as i put an ila in my design i have a placement error concerning the oserdese module I don't know how to proceed further. The behaviour I mentioned before showed up both in synthetized timing simulation and behavioural one. The bitslip logic I am using was actually based on the one you provided in Xapp, in particular I implemented the second method, the comparators one.
03-25-2019 08:12 PM - edited 03-25-2019 08:12 PM
Please share us with the placement error you are getting .
The ILA capture will help us to identify what might go wrong.