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ghaddow
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Registered: ‎06-15-2017

Ultrascale ISERDESE3 with edge timed DDR data

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Can ISERDESE3 (Ultrascale Kintex) be presented with edge timed DDR data?

(or is it necessary to either (a) phase shift the DDR clock by 90 degrees in an MMCM/PLL, or (b) add an IDELAYE3 in time mode?)

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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

There are setup and hold time for the ISERDESE3 that needs to be met. 

There is a clock alignment that is done in UltraScale automatically when you include the IDELAY : https://www.xilinx.com/support/answers/64743.html

 

Thanks,

Sandy


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sandrao
Community Manager
Community Manager
4,346 Views
Registered: ‎08-08-2007

There are setup and hold time for the ISERDESE3 that needs to be met. 

There is a clock alignment that is done in UltraScale automatically when you include the IDELAY : https://www.xilinx.com/support/answers/64743.html

 

Thanks,

Sandy


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub , Versal Blogs and the Versal Useful Resources .

------------------------------------------------------------------------------------------------

View solution in original post

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