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Visitor das_enllobu
Visitor
704 Views
Registered: ‎03-23-2018

Ultrascale Macro

Hi all, i am trying to get an upgrade of my code that fits with the ultrascale architecture and i am having a lot of problems with my MULT_MACRO, they are plenty functional in the 7Series (Virtex6 and Virtex7) but i cant find the equivalent in the ultrascale architecture. Neither in the vivado2017.3 templates nor in the primitive folders.

I have already found the Primitives but i want the little bit more of abstraction that the Macro's have.

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Community Manager
Community Manager
642 Views
Registered: ‎08-08-2007

Re: Ultrascale Macro

Looking at UG974 the UltraScale Libraries Guide it says 

IMPORTANT: Unimacros from previous generation Xilinx FPGA Architectures are not supported
in the Ultrascale architecture and have been replaced by Xilinx Parameterized Macros.

 

However I do not see a XPM equivalent to the MULT_MACRO : MULT_MACRO simplifies the instantiation of the DSP48 block when used as a simple signed multiplier.

 

The Design Entry Method for the DSP48 is recommended as Inference, you can also use Instantiation and IP. 

 

The Vivado Synthesis Guide gives details on inference of the DSP48, starting on Pg81

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf

 

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