Ultrascale RFSOC ADC and DAC AXI-stream interface Underflow and Overflow

[simonh_bwt]

Hi

I have just been looking at the RFSOC document  PG29 page 108 "Interfacing to the AXI4 -stream interface.

For a typical RFSOC application with ADC and DAC.

If the receiving logic in the PL under-runs and cannot supply the DAC with sufficent data on the AXIS i/f, or the PL receiving logic for the ADC AXIS output is unable to receive data at sufficent rate or stalls......do the ADC/DAC tile have to be reset and go through complete reset/calibration/startup sequence? Or is it possible to just reset the ADC/DAC AXIS interfaces?

Thanks SImon

[zhendon · Accepted solution]

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@simonh_bwt  已写:

Hi

I have just been looking at the RFSOC document  PG29 page 108 "Interfacing to the AXI4 -stream interface.

For a typical RFSOC application with ADC and DAC.

If the receiving logic in the PL under-runs and cannot supply the DAC with sufficent data on the AXIS i/f, or the PL receiving logic for the ADC AXIS output is unable to receive data at sufficent rate or stalls......do the ADC/DAC tile have to be reset and go through complete reset/calibration/startup sequence? Or is it possible to just reset the ADC/DAC AXIS interfaces?

Thanks SImon

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Hello，

RFSOC can be reset through AXI4-lite interface by API function. The power on sequence will be performed completely and so it needs to check the Tiles status after the reset operation. There is no dependant reset control on AXIS interface as I know.

It seems that your concern is the bandwidth of the logic interface communicated with AXIS interface. So it does't need to reset the ADC/DAC because no issue like FIFO overflow happened inside.

thanks,