UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor jangbiemee
Visitor
3,524 Views
Registered: ‎03-22-2017

Ultrascale RLDRAM3 MIG (Invalid core)

Jump to solution

Hi,

I’m implementing an RLDRAM3 interface using the RLDRAM3 MIG. The RTL simulation, synthesis, and implementation processes completed without error, but the following problems occurred after the FPGA program process:

CRITICAL WARNING: [Xicom 50-46] One or more detected MIG version registers have empty values: MIG properties will not be built.
Parameter Map Version: 0, Error Map Version: 0, Calibration Map Version: 0, Warning Map Version: 0
INFO: [Labtools 27-2302] Device xcvu190 (JTAG device index = 0) is programmed with a design that has 1 MIG core(s).
WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.

 

RLDRAM3.jpg

 

Referring to AR# 64923, I added the ’calibration_rld3.elf’ to the project. However, this problem has not been solved yet. Note that the ‘microblaze_mcs_rld3.bmm’ file does not exist in my source folder.


My platform and Vivado version information are as follows:
* Platform: Virtex UltraScale VCU110 Evaluation Platform (xcvu190-flgc2104-2-e)
* Vivado version: Vivado 16.4

Any advice is welcome. Thank you for your time.

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
6,143 Views
Registered: ‎09-20-2012

Re: Ultrascale RLDRAM3 MIG (Invalid core)

Jump to solution

Hi @jangbiemee

 

You can find the 2016.4 files here https://www.xilinx.com/member/forms/download/design-license.html?cid=0cb09bf1-1e8a-4be6-b337-884a2bfd8199&filename=rdf0338-vcu110-mig-c-2016-4.zip

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos
4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
3,510 Views
Registered: ‎09-20-2012

Re: Ultrascale RLDRAM3 MIG (Invalid core)

Jump to solution

Hi @jangbiemee

 

Did you generate the RLDRAM IP following the steps in the below doc https://www.xilinx.com/member/forms/download/design-license.html?cid=a7a77853-c687-443a-956b-b1654c09e460&filename=xtp376-vcu110-mig-c-2016-4.pdf ?

 

This error is seen if the input clock or reset to the RLDRAM IP are not proper.

 

Are you adding RLDRAM IP XCI or DCP to the project? 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Visitor jangbiemee
Visitor
3,486 Views
Registered: ‎03-22-2017

Re: Ultrascale RLDRAM3 MIG (Invalid core)

Jump to solution

Hi Deepika,

 

Thank you for your information.

 

BTW, where can I get the 'RDF0338 - VCU110 MIG Design Files (2016.4 C) zip' file? I've only found the 2016.3 version without the rld3_36b design on Virtex UltraScale Design Hub - VCU110 Development Kit.

 

Thank you.

0 Kudos
Xilinx Employee
Xilinx Employee
6,144 Views
Registered: ‎09-20-2012

Re: Ultrascale RLDRAM3 MIG (Invalid core)

Jump to solution

Hi @jangbiemee

 

You can find the 2016.4 files here https://www.xilinx.com/member/forms/download/design-license.html?cid=0cb09bf1-1e8a-4be6-b337-884a2bfd8199&filename=rdf0338-vcu110-mig-c-2016-4.zip

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos
Visitor jangbiemee
Visitor
3,444 Views
Registered: ‎03-22-2017

Re: Ultrascale RLDRAM3 MIG (Invalid core)

Jump to solution

Hi Deepika, 

 

The problem has been resolved. Especially, the 'example_design.xdc' file and 'Reference Input Clock Speed' information were helpful. Thank you very much. 

0 Kudos