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loicm88
Observer
Observer
8,771 Views
Registered: ‎03-10-2017

Ultrascale+ SLR crossing

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Hello,

 

I am targetting a xvu13p ultrascale+ fpga which has a 4 SLRs architecture.

I have a main clock at 350 MHz, and I am seeing big timing violations when crossing SLRs.

 

Is there any strategy for clocking through SLRs and for logic placement advised by Xilinx?

 

Thanks

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vemulad
Xilinx Employee
Xilinx Employee
9,999 Views
Registered: ‎09-20-2012

Hi @loicm88

 

You can create SLR based pblocks for better results.

 

You can group all timing critical paths which are crossing SLR in to a pblock and place it in a single SLR.

Thanks,
Deepika.
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sandrao
Community Manager
Community Manager
8,719 Views
Registered: ‎08-08-2007

The UFDM is a good read for this topic : https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug949-vivado-design-methodology.pdf

Specifically the section Designing with SSI Devices and SSI Technology Considerations. It has some details on SLR crossings.

Thanks,

Sandy


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loicm88
Observer
Observer
8,698 Views
Registered: ‎03-10-2017

Thanks Sandrao, I'll take a look!

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vemulad
Xilinx Employee
Xilinx Employee
10,000 Views
Registered: ‎09-20-2012

Hi @loicm88

 

You can create SLR based pblocks for better results.

 

You can group all timing critical paths which are crossing SLR in to a pblock and place it in a single SLR.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

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ADGio
Visitor
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2,084 Views
Registered: ‎07-01-2020

Hello,

and thank you for the link. I have a doubt.

I'm using a Virtex Ultrascale+ device, with 3 SLR.

At present, I use only one SRL, and the system Works, although some congestion is observed.

Due to the complexity of the design, and to the future evolution roadmap, I'm interested in spreading the design over different SRLs, in order to use better the resources.

 

The UFDM, at page 258, suggests:

- to create 2xSLR pblocks

- to create 2x SLR crossing pblocks

- use sufficient pipelining between the major hierarchies is required to ease global placement

 

If I understand correctly, I should :

1. "divide" the design elements between the SLRs, and assign each to a SLR Pblock. This división should try to minimize the crossSLR paths.

2. to add pipeling elements between the elements

As I'm usign Axi4stream interfaces, I understand the correct pipeling elements are the Axi Slice register in SLR crossing configuration.

 

My questions:

 

1. how many Axi Slice Register (with SRL crossing) should I use for each SLR crossing?

2. where should I to put it/them?

For example;

- only one, in the source Pblock

- only one, in the destination Pblock

- a pair of them, one in the source and the other in destination pblocks

- only one , in SLR-crossing Pblocks.

The document is not clear about it. Can anyone help me?

 

Thank you

regards

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