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simonh_bwt
Adventurer
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Registered: ‎02-08-2016

Ultrascale XCVU440 porting from Zynq to Ultrascale GTXE2_COMMON , GTXE2_CHANNEL , IBUFDS_GTE2 not found

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Ultrascale XCVU440 : porting from Zynq to Ultrascale GTXE2_COMMON , GTXE2_CHANNEL , IBUFDS_GTE2 not found

 

Hi,

I am porting a Zynq PHY design of a PCIe Pipe to an Ultrascale device XCVU440.

 

PLEASE NOTE I AM NOT USING STANDARD XILINX PCIE IP AS I validating a 3rd party IP for ASIC validation. I do not want to use standard Xilinx PCIe block.

 

I want to substitute the Series 7 GTX basic Serdes block for an equivalent UltraScale block.

I have read UG949, which refers to gtxe2 on page 137. However if I try and synth my design on a XCVU440 I get teh following error messages.....

 

[Netlist 29-180] Cell 'GTXE2_COMMON' is not a supported primitive for virtexu part: xcvu440-flga2892-2-i. Instance 'U1/i_wrap/i_dwc_pcie_subsystem/u_pcie_phy_wrapper/u_Xilinx_phy/pcie_gt/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.qpll_wrapper_i/gtx_common.gtxe2_common_i' will be treated as a black box, not an architecture primitive ["/blu/dm/FPGA/IP_pcie/XCVU440_RTL/dev/pcie/pcie.srcs/sources_1/imports/hacked_files/pcie_gt_top_ImA.v":14267]

 

[Netlist 29-180] Cell 'GTXE2_CHANNEL' is not a supported primitive for virtexu part: xcvu440-flga2892-2-i. 2 instances of this cell will be treated as black boxes, not architecture primitives ["/blu/dm/FPGA/IP_pcie/XCVU440_RTL/dev/pcie/pcie.srcs/sources_1/imports/hacked_files/pcie_gt_top_ImA.v":4680]

 

[Netlist 29-180] Cell 'IBUFDS_GTE2' is not a supported primitive for virtexu part: xcvu440-flga2892-2-i.  Instance 'U1/i_wrap/i_dwc_pcie_subsystem/u_pcie_phy_wrapper/clk_differ' will be treated as a black box, not an architecture primitive ["/blu/dm/FPGA/IP_pcie/XCVU440_RTL/dev/pcie/pcie.srcs/sources_1/imports/hacked_files/phy_custom_ImA.v":200]

 

 

 

How do I replace the GTXE2 modules. where is the documentation that shows how to move from 7 series devices to Ultrascale devices? which modules are equivalent to 7-series GTXE_COMMON and GTXE2_CHANNEL etc.

 

Thanks

Simon

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ashishd
Xilinx Employee
Xilinx Employee
6,303 Views
Registered: ‎02-14-2014

Hello @simonh_bwt,

 

Please check the section 'Advanced 7 Series Component Retargeting' on page #20 from below UG to get answer for your query -

https://www.xilinx.com/support/documentation/sw_manuals/ug1026-ultrascale-migration-guide.pdf

Regards,
Ashish
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ashishd
Xilinx Employee
Xilinx Employee
6,304 Views
Registered: ‎02-14-2014

Hello @simonh_bwt,

 

Please check the section 'Advanced 7 Series Component Retargeting' on page #20 from below UG to get answer for your query -

https://www.xilinx.com/support/documentation/sw_manuals/ug1026-ultrascale-migration-guide.pdf

Regards,
Ashish
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simonh_bwt
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Registered: ‎02-08-2016

Note if trying to use an PCIe PIPE IP from the IP catalog on a n XCVU440 device, you have to use a, rather than b grade device or Vivado refuses to create IP!!

 

 

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