Loot at this ultrascale(xcvu440) clock resource table, the BUFGCE component have 720.
So FPGA internal can be implement 720 different of clock frequency?
There are 720 BUFGs but I dont think its feasible to use them all for different frequencies, just thinking about it like a Math problem.
"Each Clock Region contains 24 BUFGCEs, 8 BUFGCTRLs and 4 BUFGCE_DIVs. These clock buffers share the 24 routing tracks and therefore collisions may occur resulting in unroutable designs."
You would have to get the 24 BUFGCEs into a clock region and the resources they use would have to be limited to a clock region.
"There are four GC pin pairs in each bank that have direct access to the global clock buffers, MMCMs, and PLLs that are in the CMT adjacent to the same I/O bank"
The MMCM has 6 outputs, the PLL has 4 outputs, 2 frequencies (and 2 180deg versions).
Out of the four GC pin pairs you would need 3 of them to drive the clock managers so one more to drive directly to the BUFG
That would 6 + 2 + 2 + 1 = 11 clock frequencies inputs/generated in a clock region by my estimation. You can have many more clocks in a clock region but that would a clock input from another region.