cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mufeed029
Visitor
Visitor
501 Views
Registered: ‎06-20-2019

Ultrascale plus ADC and DAC Clock frequencies

Hi Team,

I am using XCZU28DR. I found 3 different clocks in ADC and DAC section. can anyone help me find frequencies of these clocks.

I found that frequency of ADC_CLK _[P or N] / DAC_CLK_[P or N] is 245.76MHz, is it okay?

Also frequency of SYSREF_[P or N] is less than 10MHz. What is the typical value?

1. ADC_CLK_[P or N]

2. DAC_CLK_[P or N]

3. SYSREF_[P or N]

0 Kudos
1 Reply
pthakare
Moderator
Moderator
478 Views
Registered: ‎08-08-2017

Hi @mufeed029 

ADC_CLK _P/N  and  DAC_CLK_P/N are the sampling clock for the ADC and DAC. On our evaluation board , these clocks are coming from board PLLs.

Based on desired sample rate you need to program those PLLs.  Either you can do it by SCUI provided with ZCU111 documentation on web  or through SDK applications.

https://www.xilinx.com/products/boards-and-kits/zcu111.html#documentation.

Here you can programm these PLL for required sampling frequency or Refference frequency and use the internal PLL in the ADC/DAC tile.

SYSREF_P/N is required only when Multi tile Syncronization is required.  There are guidelines around this clock as follows 

Capture.PNG

This is documentated in product guide 

https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_2/pg269-rf-data-converter.pdf

245.76 Mhz you are seeing is refernece to internal PLL and output of PLL is used as sampling clock (e.g 3.93216Ghz)

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos