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Visitor
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Registered: ‎03-06-2020

Unable to force FFs into IOB on UltraScale+ Devices

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I am attempting to place the FFs of an IOBUF into the IOB on an UltraScale+ device. The input data FFs are placed in the IOB properly.

Since the IOLOGIC has no 3-state SDR register, I have followed the recommendation in <AR#62490>  but the datasheet still does not report output FFs placed in (IO). The data is a bus, so I have confirmed the tri-state FF is replicated for each bit on the bus. The Q output of the data and tri-state FFs only drive the OBUF. I have confirmed in the schematic that the property IOB is set to TRUE for the FFs. The "set_output_delay_constraint" has been set on the data bus. The Xilinx IOBUF primitive is instantiated in the HDL.

The same method was successful at placing input and output FFs in the IOB using a Virtex-7 target. I use the report_datasheet command to check for IOB placement.

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Community Manager
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Registered: ‎08-08-2007

Hi @bdel3h 

Ok I can see the same

------------------------------------------------------------------------------------------------
| Data sheet
| ----------
------------------------------------------------------------------------------------------------

Input Ports Setup/Hold

----------+---------+-----------+-------+---------------+---------+---------------+---------+----------+
Reference | Input   | IO Reg    | Delay |     Setup(ns) | Process |      Hold(ns) | Process | Internal |
Clock     | Port    | Type      | Type  | to Clk (Edge) | Corner  | to Clk (Edge) | Corner  | Clock    |
----------+---------+-----------+-------+---------------+---------+---------------+---------+----------+
clk       | data    | FDRE (IO) | -     |    -0.153 (r) | FAST    |     1.335 (r) | SLOW    |          |
clk       | data_in | FDRE (IO) | -     |     1.095 (r) | SLOW    |     0.756 (r) | SLOW    |          |
clk       | t       | FDRE      | -     |     0.139 (r) | SLOW    |     0.853 (r) | SLOW    |          |
----------+---------+-----------+-------+---------------+---------+---------------+---------+----------+


Output Ports Clock-to-out

----------+----------+--------+-------+----------------+---------+----------------+---------+----------+
Reference | Output   | IO Reg | Delay | Max Clk (Edge) | Process | Min Clk (Edge) | Process | Internal |
Clock     | Port     | Type   | Type  |    to port(ns) | Corner  |    to port(ns) | Corner  | Clock    |
----------+----------+--------+-------+----------------+---------+----------------+---------+----------+
clk       | data     | FDRE   | -     |      5.547 (r) | SLOW    |      1.615 (r) | FAST    |          |
clk       | data_out | FDRE   | -     |      8.108 (r) | SLOW    |      3.941 (r) | FAST    |          |
----------+----------+--------+-------+----------------+---------+----------------+---------+----------+

But when I look at the report (using the -name switch) I can see the OFF mentioned

iob4.PNGiob3.PNG

Thanks,
Sandy

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Community Manager
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Registered: ‎08-08-2007

Hi @bdel3h 

 

I made a simple testcase with an IOBUF and I can see the IFD and OFD placed into the IOB. 

I just the cell properties to verify the placement. IOB2.PNGIOB.PNG

 

The I included the IOB constraint into the HDL

 

attribute IOB : string;
attribute IOB of data: signal is "TRUE";

 

 

Can you check the cell properties to verify the location of the registers.

Thanks,
Sandy

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Visitor
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Registered: ‎03-06-2020

I confirmed the IOB property was set to true and the FFs were placed into XIPHY. However, the data sheet only reports the input FFs in the (IO) and not the output FFs. I will assume this is either a bug or the intended result as the tri-state FFs cannot be placed into the XIPHY on this architecture.

Capture.PNG

Capture.PNG

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @bdel3h 

Ok I can see the same

------------------------------------------------------------------------------------------------
| Data sheet
| ----------
------------------------------------------------------------------------------------------------

Input Ports Setup/Hold

----------+---------+-----------+-------+---------------+---------+---------------+---------+----------+
Reference | Input   | IO Reg    | Delay |     Setup(ns) | Process |      Hold(ns) | Process | Internal |
Clock     | Port    | Type      | Type  | to Clk (Edge) | Corner  | to Clk (Edge) | Corner  | Clock    |
----------+---------+-----------+-------+---------------+---------+---------------+---------+----------+
clk       | data    | FDRE (IO) | -     |    -0.153 (r) | FAST    |     1.335 (r) | SLOW    |          |
clk       | data_in | FDRE (IO) | -     |     1.095 (r) | SLOW    |     0.756 (r) | SLOW    |          |
clk       | t       | FDRE      | -     |     0.139 (r) | SLOW    |     0.853 (r) | SLOW    |          |
----------+---------+-----------+-------+---------------+---------+---------------+---------+----------+


Output Ports Clock-to-out

----------+----------+--------+-------+----------------+---------+----------------+---------+----------+
Reference | Output   | IO Reg | Delay | Max Clk (Edge) | Process | Min Clk (Edge) | Process | Internal |
Clock     | Port     | Type   | Type  |    to port(ns) | Corner  |    to port(ns) | Corner  | Clock    |
----------+----------+--------+-------+----------------+---------+----------------+---------+----------+
clk       | data     | FDRE   | -     |      5.547 (r) | SLOW    |      1.615 (r) | FAST    |          |
clk       | data_out | FDRE   | -     |      8.108 (r) | SLOW    |      3.941 (r) | FAST    |          |
----------+----------+--------+-------+----------------+---------+----------------+---------+----------+

But when I look at the report (using the -name switch) I can see the OFF mentioned

iob4.PNGiob3.PNG

Thanks,
Sandy

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-------------------------------------------------------------------------

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