04-13-2021 07:22 AM
I'm designing an image processing device on a Zynq Ultrascale+ board, specifically the MA-XU3-3EG-2I-D11.
I have the following problem: in my design I'm using a module (written in VHDL) which has the capabilities of receiving data form either one or two cameras. I want to use only one camera so I made the connection only for that. I tried to connect the unused inputs for the second camera to => '0'. However the design fails implementation with the following error for a number of ibufds: [Place 30-378] Input pin of input buffer Mars_XU3_i/.../g_SERDATA_RX.i_ibufds_inst/DIFFINBUF_INST has an illegal connection to a logic constant value. I checked the post-synthesis schematics and these DIFFINBUF are connected to ground.
How can I connect the inputs that I don't need in a way so that the design manages to run implementation?
Thanks in advance
04-13-2021 07:36 AM
If you have an un used input,
then don't connect it , and the synthesiser will rip it out .
04-14-2021 02:53 AM
I tried to leave the unused inputs of the upper module I need to use unconnected but Vivado gives me a critical warning before synthesis saying that the input pins are unconnected and when I run implementation it still gives me the same error as before. I think Vivado still connects the unconnected inputs to ground.
04-14-2021 03:10 AM
Do you have an IO pin of the FPGA that is not connected to anything? AND all of your unused inputs together and route the unused signal to the unused output pin. Still, this is strange. Vivado should just optimize an unused pin away.
04-14-2021 03:43 AM
I think its time for you to try to make a small test case to share so Xilinx can reproduce what your doing.
my guess is its a typo, but open to other possibilities.