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Explorer
Explorer
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Registered: ‎02-06-2018

Understanding Clock Sources for MTS in ZCU111

Hi,

 

I'm trying to implement Multi-Tile Synchronization on ZCU111 and I have some questions about the documentation.

1) As documentation says, Tile 224 (0) should be active for MTS. The tiles I'm trying to sync are Tile 226 and Tile 227. Can I just activate Tile 224 and ignore it for the rest of process?

2) I'm confused about Clock sources in the example shown in PG269 page 121. There is a LMK04208 on ZCU111 which is set to 122.88MHz by default. Is this "Analog SYSREF"? does a chip on ZCU111 supply "PL SYSREF"? for ADCs' axi_stream clocks, I'm currently generating 491.52MHz using a MMCM locked to clk_adc2 (tile 226), can I use it for PL Clock?

3) In this post , @klumsde says that the SYSREF should be less than 10MHz, Is he talking about Analog SYSREF or PL SYSREF?

4) In PG269 V2.3, page 128, and in section "Analog SYSREF Capture/Receive", it talks about XRFdc_sysrefConfig API, I have Googled it and have looked everywhere, but there is no information anywhere. Google couldn't find anything. Are there documentation about it?

 

Thank you

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Community Manager
Community Manager
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Registered: ‎08-30-2011

Hi @arashr 

1. Yes, 224 must be enabled and reference clock should be supplied to tile224 as well.

2. 122.88Mhz is from output2 of LMK04208 and it is the clock for generating clock for digital data interface such as s00_axi_aclk or m00_axi_aclk. PL_sysref is from output1 and it has the same frequency as analog sysref which is from output 1. You can refer to UG1271 figure3-18 for detail clock diagram.

3. Both

4. I think it is a typo in PG269. The correct function here should be XRFdc_MTS_Sysref_Ctrl. I will have a double-check on that and get back to you here.

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Community Manager
Community Manager
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Registered: ‎08-30-2011

Hi @arashr 

The function should be XRFdc_MTS_Sysref_Config. Though XRFdc_MTS_Sysref_Ctrl is a subfunction called by XRFdc_MTS_Sysref_Config and actually enable/disable the capture.

You can find it in driver file xrfdc_mts.c.

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/rfdc/src/xrfdc_mts.c

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Explorer
Explorer
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Registered: ‎02-06-2018

Thank you@zhendon .

I understood the answers 1,3 and 4 and I have follow-up questions on your response on question 2.

Here is the Figure 3-18 in UG1271 :

LMK04208.png

 

As per you mentioned, "PL_sysref is from output1 and it has the same frequency as analog sysref which is from output 1". So basically, I need to use Output1 for my MTS implementation. My questions are:

1) Output 1 says MPSoC DAC: SYSREF_RFSOC. What does "DAC" mean here? I am not using MTS for DACs. I'm implementing MTS for ADCs, do I still need to use this clock?

2) Where the Output0 (SYSREF_FPGA) and Output1 (SYSREF_RFSOC) are connected to? I mean they both are producing a SYSREF clock, right? I cannot find more information in UG1271. I would like to know what pins they are connected to.

3) How can I can know what is the exact frequency the "Dividers" block is putting on Output0 to Output2. Here is the code I'm using to configure LMK04208:

This is the library:

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/rfdc/examples/xrfdc_clk.c

and this function is what I call (following the design templates in the Github examples above):

unsigned int LMK04208_CKin[1][26] = {
			{0x00160040,0x80140320,0x80140321,0x80140322,
			0xC0140023,0x40140024,0x80141E05,0x03300006,0x01300007,0x06010008,
			0x55555549,0x9102410A,0x0401100B,0x1B0C006C,0x2302886D,0x0200000E,
			0x8000800F,0xC1550410,0x00000058,0x02C9C419,0x8FA8001A,0x10001E1B,
			0x0021201C,0x0180033D,0x0200033E,0x003F001F }};


	LMK04208ClockConfig(1, LMK04208_CKin);

 

I do really appreciate your help and support.

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Explorer
Explorer
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Registered: ‎02-06-2018

@zhendonI did some digging and found some clues I think. In the Schematics file, I found these:

Schematic2.png

 

Schematic.png

Which gives me the fact that the differential pins of output1 are connected to U4 and U5. Which already are connected in Vivado by default using the clocking wizard.

 

BlockDiagram.png

 

So, to summarize my questions:

1) is SYSREF_RFSOC(output1) sufficient to generate user_sysref_adc clock?

2) How may I know the exact clock rate of SYSREF_RFSOC(output1) ?

 

Thank you.

 

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Explorer
Explorer
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Registered: ‎02-06-2018

I am still trying to figure this out. I would appreciate any help.

This is my circuit:

Screenshot from 2020-10-05 15-51-46.png

sysref_in_p_0 and sysref_in_n_0 are connected to U4 and U5 pins. I don't know what its frequency is and I'm not sure how to figure it out but I trust @zhendon response to use those pins.

I'm trying to implement this circuit from PG269:

Screenshot from 2020-10-05 15-52-09.png

So PL_SYSREF_P and PL_SYSREF_N are "sysref_in_p_0" and "sysref_in_n_0" in my design. The clock of the D flip-flop is 491.52MHz coming from a clocking wizard locked to clk_adc.  Is this a correct circuit for the user_sysref_adc?

 

Thank you.

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Moderator
Moderator
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Registered: ‎04-18-2011

For ZCU111 FPGA_REFCLK on the board is the external PL ref_clk. It is 122.88Mhz. 

We expect this to come from outside. 

If you are going to multiply it up using the MMCM the SYSREF on the PL side must by captured by a flop in the 122.88MHz domain followed by a flop in the 491.54Mhz domain. 

this is shown in this figure. 

klumsde_0-1601940126972.png

 

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Explorer
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Registered: ‎02-06-2018

Hi @klumsde , Thank you.

When you say "We expect this to come from outside.", by "outside", do you mean LMK04208 which is onboard or I need an oscillator sitting next to ZCU111?

Are these clocks commented correctly on the diagram below?

ClockDiagram.png

In the documentation, it says "The AXI4-Stream clocks for the Zynq ® UltraScale+TM RF Data Converter core must be generated from the PL clock input and not from the clock outputs from the core itself.". Currently, I am using the clock outputs of the core to generate AXI clocks (photo below). Does this mean that I should redesign the clocking circuit to use PL_CLK instead of clk_adc?

Screenshot from 2020-10-05 17-26-33.png

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Community Manager
Community Manager
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Registered: ‎08-30-2011

HI @arashr 

Sorry for my late response. I was on vacation last week.

And I made a mistake in my last reply. output1 of LMK04208 actually generated the dedicated analog sysref. Output0 generates the PL_sysref which is connected to the general-purpose pin of FPGA and which will be routed to the PL_sysref port of RFSoC IP. Both clocks should have the same frequency.  Sorry for the confusion.

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