06-16-2020 02:17 AM
In the ug583 v1.18 (p29), "Xilinx recommends placing the 0402 capacitors directly under the FPGA footprint on the oppose site of the board. This
minimizes spreading inductance and result in maximum efficiency."
So Xilinx recommend for the 10µF capacitors, to be placed under the FPGA in the bottom side. In schematics, the decoupling sheets of for VCU118 and VCU129, I see only 4.7µF for decoupling. I assume you changed 10µF to 4.7µF and I'm interessed to know why.
And, looking the PCB layout of this two boards, I saw absolutly no decoupling capacitor directly under the FPGA footprint. All capacitor are on the periphery of the FPGA. There is some reason to keep free of any components under the FPGA?
06-18-2020 02:35 AM
We do not recommend customers to use the Eval Boards as a reference for designing their boards. Refer to PCB design guide which is UG583 since the recommendations in this guide are based on characterized data.
The Eval Boards are designed well before the chip arrives and so may or may not meet the recommendation in the PCB design guide.