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Registered: ‎02-04-2019

Versal FPGA AIE to PL logic bit width rate matching and throughput?H


I am looking at the Versal 1902 AIE column to PL logic interface throughput, if PL only run 250MHz, (vs. AIE side 1GHZ), using 128-bit wide streaming bit width, can the rate match to 1G HZ 32-bit wide stream? aka. can the PL logic side fully match the throughput of the AIE column total throughtput of 24GBps south, 32GBps north?



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Xilinx Employee
Xilinx Employee
Registered: ‎02-24-2017

Hi Weihong.

If PL only run using a 250MHz the best BW we can have is using a 128b stream on the PL Side. Bandwidth can be 4GB/s per stream, the same rate of an internal 1GHz 32b stream.

But to do so it will uses 2 native PL-AIE 64b stream interfaces connected to 1 internal 32b stream. It means we can have up to 4x 128b streams going into the AIE PL interface Tile (connected to 4 internal streams) and 3x128b streams going out from the AIE PL Interface Tile (connected to 3 internal streams). -> 16GB/S north, 12GB/s south.

when using 32b interfaces even running at 500MHz and using all the PL stream of a column : you will have the same cumulated bandwidth. 

You can only have the 32GB/s (24GB/s) bandwidth using 64b interface running at 500MHz.

Another thing to know : Inside the AIE Interface Tile, there is an AXI Stream interconnect used to connect the PL interfaces, west and east AIE interface Tile AXIS Interconnects and AIE column. This AXIS interconnect has :

  • 8(6) 32b stream ports from (to) PL interfaces : 32GB/s (24GB/s)
  • 4(4) 32b stream ports from (to) west interface tile : 16GB/s (16GB/s)
  • 4(4) 32b stream ports from (to) east interface tile : 16GB/s (16GB/s)
  • 6(4) 32b stream ports to (from) AIE column : 24GB/s (16GB/s)

Cumulated throughput between the AIE column and AIE interface tile is also limited by the interconnect : 24GB/s north, 16GB/s south even using 64b PL interfaces.

To resume :

  • 1 PL interface 128b stream @250MHz bandwidth equal 1 internal 32b stream @1HGz.
  • Cumulative bandwidth of 128b PL interfaces (16GB/s North, 12GB/s South) in a column is less than AIE interface tile - AIE column bandwidth (24GB/s North, 16GB/s South).