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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

Versal and Ultrascale Architecture Useful Resources : Please read before posting questions

Versal and UltraScale Architecture - Useful Resources

The Versal and Ultrascale Architecture board covers queries on Architecture, SelectIO, Power (non-estimation queries), Thermal, System Monitor, PCB, Packaging for Versal, Ultrascale+, Ultrascale family along with the RF section in Zynq UltraScale+ RFSoC.


Summary

  1. Versal Resources
  2. Zynq UltraScale+ RFSoC
  3. Zynq UltraScale+ MPSoC
  4. UltraScale/UltraScale+ Resources 
  5. Blogs

1. Versal Resources

The Versal Design Process Hubs are rolling out to assist users find the relevant information to the design step that you are working on.

System and Solution Planning 

Board System Design

System Integration and Validation 

AI Engine Development 

 

The Versal Device Tutorials are available on Github.

When asking your question, it is useful to post the question on the most suitable board in order to improve the Community's ability to help with your questions. Add "Versal" tag to your posts for added visibility. 

Here are some links to boards that may be more suitable for your questions.

Memory and NoC board covers questions on DDR4, LPDDR4, NoC, Hardened Memory Controllers

ACAP Boot and Config covers questions to include secure and non-secure boot flow including programming the boot device (OSPI, QSPI, JTAG, SD/eMMC, NAND, NOR), bootrom, FSBL, PLM, loading of the bitstream, fallback/multi-boot, programming of eFUSEs and BBRAM

Ethernet board covers Standard Ethernet IP and Embedded Ethernet issues including hardened blocks in Versal. This includes IPs' functionalities, IPs' GUI options, IPs' implementations, IP related timings, drivers (ie, AXI Ethernet standalone/linux driver, emacs standalone driver, MACB driver) and LWIP related questions. 

PCIe board covers questions on PCIe and CPM for Versal 


2. Zynq UltraScale+ RFSoC Resources

When designing for the Zynq UltraScale+ RFSoC devices a really useful resource is the Design Hub which brings together the relevant documentation: https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0087-zynq-rfsoc-hub.html

Additionally we have outlined the following documents and resources for designing with RFSoC. 

Resources Specific to RF Data Converters:

The RF Data Converter IP and SW Driver are documented in PG269 

RF PCB guidelines are contained in Chapter 3 of the Ultrascale PCB Design Guide UG583

For help with understanding key RF data converter metrics please refer to this white paper: WP509

To get access to data converter performance data, you can apply for access to the Characterization Data Lounge.

You can also use this spreadsheet to help with RF frequency planning in your design.

We support 3 Customer Evaluation Boards for RFSoC.

 

ZCU111 targets a RFSoC Gen1 8T8R device

ZCU208 targets a RFSoC Gen1 8T8R device

ZCU216 targets a RFSoC Gen1 16T16R device

 

These boards come with an Evaluation design for the RF Data Converters. This evaluation design can connect to a labview GUI for generating DAC waveforms and Capture of ADC data.

The Evaluation Design for ZCU111 has it’s own User Guide, UG1287

For debugging RF designs we also provide the RF Analyzer, which allows debug of the RF data converters on any device  / any board.

The RF Analyzer UI is described in UG1309

 

RF Blogs:

 

There a number of Design and Debug Blogs on RF Data Converters.

Getting in Synch with RF Data Converters - This goes in depth on the SW drivers for RFDC

Analyze This: Unboxing the RF Analyzer Tool Part One – this details the RF Analyzer hardware design

Analyze-That-Unboxing-the-RF-Analyzer-Tool-Part-2 – This is a hands on guide to use the RF Analyzer GUI on your board

Getting-in-Synch-with-RF-Data-Converters – this Blog explains how our Multi Converter Synchronization Solution works in HW and SW

RF-Data-Converter-IP-Example-Simulation-Walkthrough – This Blog details the IP Example Simulation

 

 

Xilinx Wiki:

Xilinx provides how-to articles on the Xilinx Wiki for RFSoC.

Resources Specific to Zynq Ultrascale+ Architecture:

  1. Architecture:
    1. Clocking Resources UG: UG572
    2. Clocking Wizard IP PG: PG065
    3. CLB UG: UG574
  2. SelectIO: 
    1. SelectIO UG: UG571
    2. SelectIO Wizard IP PG: PG188  
  3. Power/PCB Design: 
    1. Power:
      1. Queries on Estimation in XPE/Report Power: Vivado Debug and Power Estimation Tools
      2. XPE UG: UG440
      3. 7-Steps to an accurate worst-case analysis using XPE: XAPP1348
      4. Vivado Report Power UG: UG907
      5. Vivado Report Power Tutorial: UG997
      6. Power Delivery: https://www.xilinx.com/products/technology/power.html#partners
      7. S-Parameter Models for PDN Simulations: Open a Service Request
    2. PCB Design:
      1. PCB UG: UG583
      2. PCB Design Rules for BGA's: UG1099
      3. Device Pinout: https://www.xilinx.com/support/package-pinout-files/zynq-ultrascale-plus-pkgs.html
      4. Ultrascale+ Schematic Checklist: XTP427
  4. Thermal: https://www.xilinx.com/products/technology/power.html#thermal
  5. System Monitor
    1. System Monitor UG: UG580
    2. System Management Wizard: PG185
  6. Packaging UG: UG1075
  7. Other topics than the above: Post in the respective boards. For e.g.
    1. PS Related and AXI: Processor System Design and AXI
    2. Device Configuration: ACAP and SoC Boot and Configuration
    3. Memory: Memory Interfaces and NoC 
    4.  PCIe:  PCIe and CPM
    5. Ethernet: Ethernet
    6. Video/Audio: Video and Audio
    7. GT's: Serial Transceivers
    8. DSP: AI Engine, DSP IP and Tools
    9. BRAM/FIFO/JESD/Aurora/CPRI: Xilinx IP Catalog
    10. Logic Analyzer/XPE/Report Power:  Vivado Debug and Power Estimation Tools
    11. Ultrascale+/Ultrascale Evaluation Boards: Xilinx Evaluation Boards

3. Zynq UltraScale+ MPSoC Resources

When designing for the Zynq UltraScale+ MPSoC devices a really useful resource is the Design Hub which brings together the relevant documentation : https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0070-zynq-mpsoc-design-overview-hub.html

  1. Architecture:
    1. Clocking Resources UG: UG572
    2. Clocking Wizard IP PG: PG065
    3. CLB UG: UG574
  2. SelectIO: 
    1. SelectIO UG: UG571
    2. SelectIO Wizard IP PG: PG188
  3. Power/PCB Design: 
    1. Power:
      1. Queries on Estimation in XPE/Report Power: Vivado Debug and Power Estimation Tools
      2. XPE UG: UG440
      3. 7-Steps to an accurate worst-case analysis using XPE: XAPP1348
      4. Vivado Report Power UG: UG907
      5. Vivado Report Power Tutorial: UG997
      6. Power Delivery: https://www.xilinx.com/products/technology/power.html#partners
      7. S-Parameter Models for PDN Simulations: Open a Service Request
    2. PCB Design:
      1. PCB UG: UG583
      2. PCB Design Rules for BGA's: UG1099
      3. Device Pinout: https://www.xilinx.com/support/package-pinout-files/zynq-ultrascale-plus-pkgs.html
      4. Ultrascale+ Schematic Checklist: XTP427
  4. Thermal: https://www.xilinx.com/products/technology/power.html#thermal
  5. System Monitor
    1. System Monitor UG: UG580
    2. System Management Wizard: PG185
  6. Packaging UG: UG1075
  7. Other topics than the above: Post in the respective boards. For e.g.
    1. PS Related and AXI: Processor System Design and AXI
    2. Device Configuration: ACAP and SoC Boot and Configuration
    3. Memory: Memory Interfaces and NoC 
    4.  PCIe:  PCIe and CPM
    5. Ethernet: Ethernet
    6. Video/Audio: Video and Audio
    7. GT's: Serial Transceivers
    8. DSP: AI Engine, DSP IP and Tools
    9. BRAM/FIFO/JESD/Aurora/CPRI: Xilinx IP Catalog
    10. Logic Analyzer/XPE/Report Power:  Vivado Debug and Power Estimation Tools
    11. Ultrascale+/Ultrascale Evaluation Boards: Xilinx Evaluation Boards

4. UltraScale/UltraScale+ Resources

When designing for theUltraScale/UltraScale+ devices a really useful resources are the Design Hub which brings together the relevant documentation: https://www.xilinx.com/support/documentation-navigation/design-hubs.html

  1. Architecture:
    1. Clocking Resources UG: UG572
    2. Clocking Wizard IP PG: PG065
    3. CLB UG: UG574
  2. SelectIO: 
    1. SelectIO UG: UG571
    2. SelectIO Wizard IP PG: PG188
  3. Power/PCB Design: 
    1. Power:
      1. Queries on Estimation in XPE/Report Power: Vivado Debug and Power Estimation Tools
      2. XPE UG: UG440
      3. 7-Steps to an accurate worst-case analysis using XPE: XAPP1348
      4. Vivado Report Power UG: UG907
      5. Vivado Report Power Tutorial: UG997
      6. Power Delivery: https://www.xilinx.com/products/technology/power.html#partners
      7. S-Parameter Models for PDN Simulations: Open a Service Request
    2. PCB Design:
      1. PCB UG: UG583
      2. PCB Design Rules for BGA's: UG1099
      3. Device Pinout: https://www.xilinx.com/support/package-pinout-files/ultrascale-pkgs.html
      4. Ultrascale+ Schematic Checklist: XTP427
      5. Ultrascale Schematic Checklist: XTP344
  4. Thermal: https://www.xilinx.com/products/technology/power.html#thermal
  5. System Monitor
    1. System Monitor UG: UG580
    2. System Management Wizard: PG185
  6. Packaging UG: UG575
  7. Other topics than the above: Post in the respective boards. For e.g.
    1. Device Configuration: FPGA Configuration
    2. Memory: Memory Interfaces and NoC 
    3.  PCIe:  PCIe and CPM
    4. Ethernet: Ethernet
    5. Video/Audio: Video and Audio
    6. GT's: Serial Transceivers
    7. DSP: AI Engine, DSP IP and Tools
    8. BRAM/FIFO/JESD/Aurora/CPRI: Xilinx IP Catalog
    9. Logic Analyzer/XPE/Report Power:  Vivado Debug and Power Estimation Tools
    10. Ultrascale+/Ultrascale Evaluation Boards: Xilinx Evaluation Boards

5. Blogs

Blog posts related to this Board

Thanks,

Sandy


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If starting with Versal take a look at our Versal Design Process Hub , Versal Blogs and the Versal Useful Resources .

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