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Visitor achen58
Visitor
290 Views
Registered: ‎02-24-2019

Vewing output of High Speed Select I/O Wizard

I am having trouble seeing the output of the high speed select i/o wizard. Is it my wizard design or testbench design that is causing output of the wizard to be zeros? Attached are my wizard settings and testbench waveform. 

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2 Replies
Moderator
Moderator
248 Views
Registered: ‎08-08-2017

Re: Vewing output of High Speed Select I/O Wizard

Hi @achen58 

Did you try generating IP example design with this HSSIO configuration settings ?    Is  same behaviour persist there too?

Additionally please let us know the VIVADO version and Device part number to check the example design simulation at our end. It will also be helpful if you share your testbench file.

 

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Visitor achen58
Visitor
226 Views
Registered: ‎02-24-2019

Re: Vewing output of High Speed Select I/O Wizard

Hi @pthakare 

I actually did more reading on the HSSIO guide and I ended up checking on the FIFO read enable user control and RIU clock from PLL. I ran simulation with just these two seletions added and the output was present. Right now, I am confused on how to interpret the output. Here is a screen shot of the simulation. 

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